V-Class servers use a shared-memory architecture to provide
high-performance. This allows the developer, compilers, and applications
to view the system as processors sharing a large physical memory
and high-bandwidth I/O ports.
Message passing hardware provides ahigh performance for applications
developed using a messaging scheme known as the Message Passing
Interface (MPI). For more information concerning message passing,
see the chapter entitled Chapter 4 “Data mover”
for more information.
Compilers use shared memory to provide automatic, efficient
parallelization, while viewing memory as a single contiguous virtual
address space.
The Hyperplane crossbar provides high-bandwidth, low-latency
nonblocking access from processors and I/O channels to
the system memory. It prevents the performance drop-off associated
with systems that employ a system-wide bus for processor and I/O
memory traffic.
Sequential memory references (linearly ascending physical
address) to shared memory are interleaved across up to eight memory
boards on a 32-byte basis. See the chapter Chapter 2 “Physical address space” for more information.
With all processor references to memory, copies of the accessed
data are encached into either the instruction or data caches of
each processor. If the processor making the memory reference modifies
the data and if another processor references that same data while
a copy is still in the first processor cache, a condition exists
whereby the data has become stale. The V-Class hardware continually
works to ensure that the second processor does not use an outdated
copy of the data from memory. The state that is achieved when both
processors' caches always have the latest value for the
data is called cache coherence.
To maintain updated coherent copies, V-Class servers operate under
the following rules:
Any number of read encachements of
a cache line can be made at a single time. The cache line can be
read-shared in multiple caches.
To write (store) data into a cache line, the cache
line must be "owned" exclusively by the processor.
This implies that any other copies must be invalidated.
Modified cache lines must be written back to memory
from the cache before being overwritten.
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