Physical addresses

The PA-8200 processor is an implementation of the 64-bit PA-RISC 2.0 architecture. The processor translates all 32- and 64-bit, virtual and absolute addresses to 64-bit physical addresses. External to the PA-8200 chip, however, only 40 bits of the 64-bit physical address are implemented.

The I/O system uses controllers that have fewer than 40 address bits. The mapping of I/O addresses to the corresponding 40-bit physical address space occurs in the EPIC I/O subsystem.

V-Class server processors have four addressable physical address regions. These are:

Coherent memory space—Memory used for programs and data and available to every processor. This is the bulk of the memory space.
Core logic space—The space occupied by a group of hardware registers that comprises the system core logic function and is accessible to all processors within the system.
Local I/O space—The space occupied by the PCI buses and prefetch and context RAM CSRs associated with input and output devices within the system.
Non-I/O CSR space—The space occupied by the group of all other CSRs within the system.

Figure 2-1 “Physical address space partitioning” shows how the address space is partitioned.

Figure 2-1 Physical address space partitioning

The left side shows the PA-8200 64-bit address map, and the right shows the 40-bit external address map used by the system. The two regions labeled unmapped space exist in the 64-bit physical address space but do not exist for the 40-bit physical address space.

Physical addresses

Technical documentation

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