Core logic space

Core logic space is used to access core logic hardware (EEPROM, SRAM, and core logic CSRs) and is only accessible within the system. The processor has a fixed decode for this space. Bits 8 through 15 of the 40-bit physical address are ignored for address decoding.

Figure 2-8 40-bit core logic space format

The addresses contain a 24-bit offset used as the core logic bus address. The EPAC translates from the physical addresses to core logic bus addresses. It also splits 64-bit requests into two, 32-bit requests. The EPUC translates the core bus address to utility address. See Figure 2-9 “Core logic address translation”.

Figure 2-9 Core logic address translation

Core logic space is further partitioned for EEPROM, SRAM, and CSR Space. Table 2-6 “Core logic space partitions” shows the address ranges for each of these partitions.

Processor-dependent code (PDC) space is accessed using the core logic bus attached to each processor. A PDC space access is not routed through the Hyperplane crossbar.