CSR access

There are three packet routing methods used for accessing CSRs:

Processor-local
EPAC-local
Node

The 40-bit physical address determines which access method will be used.

Processor-local access

Processor-local accesses reference CSRs that reside in the processor issuing the request. These accesses are sent out and brought back into the requesting processor on its Runway bus. The EPAC, which is also connected to the Runway bus, ignores the request. The processor online bits of the processor agent are not checked for processor-local accesses.

EPAC-local access

EPAC-local accesses are accesses to CSRs that reside in the EPAC physically connected to the processor that is issuing the request. These accesses are identified as EPAC-local and are not sent to the Hyperplane crossbar. Table 2-7 “Field specifications for system access” shows which fields must be specified for EPAC-local addressing.

This method accesses processor-specific CSRs that reside in an EPAC. All processor-specific EPAC CSRs are identified as having bit 2 of the Chip field set. When the EPAC detects a processor-specific page, it forces bit three of the page field according to the processor issuing the request.




	NOTE: The EPAC online field of the System Configuration CSR is not checked for EPAC-local accesses.

System accesses

System accesses are used to access CSRs throughout the system. If the access is to an EMAC, the DXbr field routes the request to the proper EMAC. The EMAC Online field of the source EPAC System Configuration register is checked to ensure the destination EMAC is online. A high-priority machine check trap will result if the destination EMAC is not online.

If the access is to an EPAC, EPIC, or processor, the request is first routed to the EMAC specified by the Intermediate EMAC field of the EPAC Configuration CSR. The EPAC Online field of the source EPAC System Configuration CSR is checked to ensure the destination EPAC is online. If the destination EMAC is not online, an HPMC results.

Table 2-7 Field specifications for system access

Field	Specification
Bits 0:5	0x3F
Local EPAC	0
SXbr	X
DXbr	Destination Hyperplane crossbar port
Chip	Destination chip

Access to nonexistent CSRs

It is possible to send a request to a CSR in a controller that is not online. Online bits are implemented for processors, EPACs, EMACs, and EPICs. Memory uses existence bits.

Accesses to nonexistent CSRs terminate in one of the following ways:

Requests with a response to a CSR covered by an online bit result in an error response being returned to the processor. The processor issues a high-priority machine check interrupt.
Requests without a response to a CSR covered by an online bit result in a time-out when the next synchronization operation is performed. The synchronization time-out results in a high-priority machine check interrupt.
Requests with a response to a CSR not covered by an online bit result in a time-out. The request time-out results in a high-priority machine check interrupt.
Requests without a response to a CSR not covered by an online bit result in a time-out when the next synchronization operation is performed. The synchronization time-out results in a high-priority machine check interrupt.

System Configuration register

The System Configuration register specifies system configuration parameters. The register is replicated on the EPAC and EMAC, but only fields used by each controller type are implemented for a particular controller. Therefore, not all fields exist on an EPAC or EMAC.

Figure 2-12 “System Configuration register definition” shows the generic format of the register. All fields are written to by a write access and read from by a read access. All fields are unaffected by reset unless specified.

Figure 2-12 System Configuration register definition

The bits and fields of the System Configuration register are defined as follows:

EPAC online field (bits 0:7)—Specifies which EPACs are accessible. These bits are used to validate all I/O space and local CSR Space requests. The field is cleared by reset.
EMAC online field (bits 8:15)—Specifies which EMAC ASICs are accessible. These bits are used to validate all Coherent Memory Space and CSR Space requests. The field is cleared by reset.
EMAC exist field (bits 16:23)—Indicates which EMAC ASICs exist in the system. These bits are used by software to initialize the EMAC online field. The field is initialized by reset. A CSR write is ignored.
VI mask field (bits 35:41)—Specifies the Virtual Index bits generated by the PA-8200 processor that are masked (forced to zero).
Alternate TLB-U bit enable bit (bit 45)— Enables checking for coherent accesses to noncoherent semaphore memory.
Memory board routing bit (bit 46)—Selects the coherent memory request to the memory board routing function. When the bit is zero, even coherent memory requests are routed to even memory boards and odd requests to odd boards. When the bit is one, even coherent memory requests are routed to odd memory boards and odd requests to even boards.
MSB row select bit (bit 47)—Selects which bit of the 40-bit physical address is the most significant bit of the three-bit row selection information.
Banks per memory board bit (bit 53)—Specifies whether two or four banks exist per memory board.
Normal memory interleave field (bits 54:55)—Specifies the number of even/odd memory board pairs which normal interleaving should span.

EPAC Configuration register

Each EPAC has one Processor Agent Configuration register which specifies information about the EPAC. Each EPAC can be configured differently.

Figure 2-13 “EPAC Configuration register definition” shows the format of the EPAC Configuration register. All fields of the register are read by a read access.

Figure 2-13 EPAC Configuration register definition

The bits and fields in the EPAC Configuration register are defined as follows:

EPAC part number field (bits 0:15)—Specifies the part number for the EPAC. A write is ignored and a read returns the hard-wired value.
EPAC version field (bits 16:19)—Specifies the version for the EPAC. A write is ignored and a read returns the hard-wired value.
EPIC online bit (bit 55)—Set by software to allow CSR accesses to the EPIC. The bit is cleared by reset.
EPIC installed bit (bit 56)—Specifies whether an EPIC ASIC is connected to the EPAC. A value of one indicates an EPIC is installed. This bit is read only.
EPIC interface width bit (bit 57)—Specifies whether a 32-bit or 16-bit interface exists between the EPIC and EPACs. A value of one indicates a 32-bit interface, a value of zero indicates 16-bit. This bit is read only.
Intermediate EMAC field (bits 58:60)—Specifies the physical EMAC used by the EPAC when routing a packet to another EPAC. Any EMAC installed in the system can be specified and packet routing will function properly.
EPAC identification field (bits 61:63)—Specifies the identification number for the physical EPAC. The value is obtained from pins on the EPAC. A write to this field is ignored and a read access will return the value of the pins.

EPAC Processor Configuration register

Each EPAC has a Processor Configuration register that contains specific information about the EPAC processor. Each processor attached to the EPAC can be configured differently. Figure 2-14 “EPAC Processor Configuration register definition” shows the format of the EPAC Processor Configuration register. All fields of the register are read by a read access.

Figure 2-14 EPAC Processor Configuration register definition

The bits and fields in the EPAC Processor Configuration register are defined as follows:

Subcomplex mask field (bits 0:15)—Determines which processors should receive broadcasted transactions.
Implementation dependent field (bits 55:57)—Used by low-level implementation dependent software. The value in this field should not be modified during normal operation.
Processor online bit (bit 58)—Indicates that the processor is accessible. The value is initialized to the value of the processor installed bit.
Processor installed bit (bit 59)—Indicates that the processor is installed. The value of this bit comes directly from a pin on the EPAC. Writes to this bit are ignored; a read access will return the value of the input pin.
Processor identification field (bits 60:63)—Specifies the identification number for the physical processor. The value read is obtained by concatenating the three EPAC ID pins and bit 27 of the 40-bit address used to read the register. A write to this field is ignored and a read access will return the value of the pins/address bit.

EPAC Memory Board Configuration register

Each EPAC has a Memory Board Configuration register that specifies the memory block to memory board mapping. Figure 2-15 “EPAC Memory Board Configuration register definition” shows the format of the register. All fields are written by a write access and read by a read access. Reset has no effect. Writes to reserved bits are ignored and reads to reserved bits return the value zero.

Figure 2-15 EPAC Memory Board Configuration register definition

The three-bit memory block generated by the memory block interleave generation logic indexes into one of the eight memory board fields of the Memory Board Configuration register.

The memory board fields specify the most significant two bits of the physical memory board. The least significant bit of the memory block index is the least significant bit of the physical memory board. This forces even memory blocks to be mapped to even memory boards and odd memory blocks to odd memory boards.

EMAC Configuration register

Each EMAC has a Configuration register that contains specific information. Each EMAC can be configured differently.

Figure 2-16 “EMAC Configuration register definition” shows the format of the register. All fields of the register are read by a read access.

Figure 2-16 EMAC Configuration register definition

The bits and fields in the EMAC Configuration register are defined as follows:

EMAC part number field (bits 0:15)—Specifies the part number for the EMAC chip. A write is ignored and a read returns the hard wired value.
EMAC version field (bits 16:19)—Specifies the version for the EMAC chip. A write is ignored and a read returns the hard wired value.
Implementation dependent field (bits 20:42)—Used by low-level implementation dependent software. The value in this field should not be modified during normal operation.
Refresh period field (bits 43:54)—Indicates how often refresh occurs. For SDRAMs that need to be refreshed every 15.6us, this value should be set to 0x3a8, which is 936 half clocks.
Refresh frequency field (bits 55:56)—Controls the operation of refresh. The value of this field after reset is 3.
Implementation dependent field (bits 57:60)—Used by low level implementation dependent software. The value of these bits should not be modified during normal operation.
EMAC identification field (bits 61:63)—Specifies the identification number for the physical EMAC. The value is written by software.

EMAC Memory Row Configuration register

Associated with each EMAC are four banks of memory, each bank having up to eight rows of SDRAMs. A table maps the row specified in the physical address to a physically installed row of SDRAMs. The four banks of memory controlled by an EMAC have the same memory row mapping.

Each EMAC has a register that specifies the memory row mapping. The format of the register is shown in Figure 2-17 “Memory Row Configuration register definition”. All fields are written by a write access and read by a read access. Reset has no effect. Writes to reserved bits are ignored and reads to reserved bits return the value zero.

Figure 2-17 Memory Row Configuration register definition

The 3-bit row field of a physical address indexes one of the eight sets of row fields of a Memory Row configuration register.

The bits and fields in the EMAC Memory Row Configuration Register are defined as follows:

16 Mbit exist bits—Indicate that a DIMM with 16-Mbit SDRAMs exists for the row. The field checks memory existence access.
64 Mbit exist bits—Indicate that a DIMM with 64-Mbit SDRAMs exists for the row. The field checks memory existence access.
Installed row fields—Map the row specified by the physical address to the physical memory row.