Processor caches

Each processor has two caches: a data cache and an instruction cache, referred to as dcache and icache, respectively. These caches are two Mbytes in size each. The data cache may be modified; the instruction cache may not.

Whenever data is loaded into the data cache (this process is called move-in), the processor can modify it there. If another processor makes a data reference to the same item while the copy is still in the first processor's cache, hardware ensures that the original item and the copy are identical to maintain coherency.

Often more than one memory line is encached. For data references, all cache lines of the referenced page can be imported, and for instruction references, all lines in the referenced page and the following page (both virtual and physical) can be imported. A flush cache, purge cache, or purge TLB instruction stops any subsequent move-in operations to that page until another reference is made.

Each processor supports speculative execution of code, which is enabled with virtual address translation. Speculative execution allows cache move-in of any coherent memory line, provided that the virtual-to physical address translation of the memory line is in the processor translation lookaside buffer (TLB). Also, the virtual-to-physical translation bit in the processor status word must be set and the TLB entry must have the Uncacheable bit (U bit) cleared. See the section “PA-8200 TLB Entry U-bit”.

Caches are flushed by one of two methods:

All cache operations are issued with a single processor instruction. These include:

The FDC and PDC instructions have identical functionality on the PA-8200. Both operations flush cache lines from the data caches of all processors in the system. FDC and PDC instructions write data from dirty cache lines back to memory.

The FDCE and FICE instructions flush an entry from the executing processor's cache only. If the cache line in the data cache is dirty, it is written back to local memory.

	NOTE: Always follow cache flush instructions by a sync instruction to ensure that all flushes are complete.