Cache coherence causes the system to behave as if it had a
single data cache and a single instruction cache (logically) for
all processors. Since there are many processors and, therefore,
multiple data caches, each processor must cross-interrogate for
current data and broadcast purges and flushes (except for FDCE and
FICE).
All coherent data references are satisfied using cache coherence
checks. These checks ensure that the data has remained coherent
since it was moved in. Cache coherence checks are performed on write
buffers in order to ensure proper ordering of storage accesses.
Accelerated cache coherence |
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V-Class servers employ the Multi-Level Runway bus (MLR) mode
on PA-8200 processors for coherent memory transfers. This mode allows
multiple runway buses in the same system to have a coherent view
of memory.
In MLR mode during read requests, the processor does not take
ownership of a memory line until the EPAC accesses memory and the
EMAC sends a response back to the processor. When the processor
receives the response, it checks to see if the line is in its outbound
queue. If the processor does have the data in this queue, it issues
a write back to the EPAC.
Accelerated cache coherence is employed, because some applications
that do not take the MLR mode into account could use certain instruction
sequences. These would degrade system performance by causing increased
memory access latency and bandwidth.
Accelerated cache coherence hardware detects whether the processor
could have any data in its outbound queue. If the outbound queue
is empty, it tags the read request so that the EMAC determines the
queue is empty and does not need to send a flush to the processor.
Since the EMAC does not have to flush the queue, it can send the
data to the processor immediately. Without accelerated cache coherence,
the read transfer would require two memory accesses.
When several processors reference the same memory line, the
EMAC for that line maintains a tag for each line of main memory.
The tag keeps track of which processors are sharing the line and
how they are accessing it. Using this tag, the EMAC forwards transactions
to a limited number of processors rather than to all of them. These
tags are separate from the cache tags maintained by the processor.
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