Address aliasing

Equivalent aliasing

Equivalent aliases are virtual addresses for which offset bits 40 through 63 and space bits 36 through 47 are the same. This means that the offset portions of the addresses differ by a multiple of 16 Mbytes. A virtual address that is equal to the absolute address it maps is an equivalent mapping; this is a simple case of equivalent aliasing.

The PA-RISC architecture allows unrestricted equivalent aliasing. There may be any number of equivalent aliases, with any combination of mappings (read-only, writable, etc). The V-Class server architecture completely supports this type of aliasing.

Nonequivalent aliasing

Nonequivalent aliases do not satisfy the requirements for equivalent aliases. If nonequivalent aliases exist, the PA-RISC architecture requires that they must all be read-only. If a writable translation is required, any aliases that are not equivalent to the writable translation must be removed from the page table and flushed from the TLB before the translation is made writable.

	NOTE: The V-Class architecture does not support nonequivalent aliasing regardless of whether the aliases are read-only or not.

Nonequivalent aliasing on V-Class servers may cause a hardware virtual index error that results in an HPMC. Only processor coherent memory references cause virtual index errors; processor instruction fetches and references from I/O adapters can not cause these errors. The error only occurs when the following two conditions are met:

Nonequivalent aliasing can not be used on V-Class servers. Furthermore, to prevent the unintentional introduction of nonequivalent aliases, special cache flushing protocol must be observed when unmapping a physical page and remapping it at a different virtual address and when mixing absolute accesses and virtual accesses to the same page.

Before a page is remapped, it must be completely flushed from all data caches in the system.

This cache flushing must use FDC to avoid virtual index errors. Flushing the data cache with FDCE is not sufficient to avoid virtual index errors, because data may be left in other processors' caches. Even flushing the page with FDCE on every processor is insufficient, because the memory system maintains coherency tags that are unaffected by FDCE.

The virtual address of the FDC is irrelevant; only the absolute address to which it is mapped is important. This means that memory can be flushed to prevent virtual index errors without knowing how it was previously mapped.

Instruction aliasing

The V-Class server supports instruction aliasing. If none of the aliases allows data references (i.e., all aliases are executable only or allow no access at all), arbitrary aliasing is allowed, whether equivalent or not. The V-Class server handles data and instruction references completely separately, so there can be arbitrary instruction aliasing. Instruction cache coherence must be maintained in software.

	NOTE: Any aliases that allow data references must be equivalent aliases.