Noncoherent semaphore operators

The V-Class server supports six semaphore operators not defined in the PA-RISC architecture. These special operators may enhance semaphore operations in some applications, because they operate directly on semaphore variables located in unencacheable memory pages (pages with the U-bit set in the TLB entry; see the section “PA-8200 TLB Entry U-bit”). They do not accelerate the semaphore into the data cache.

These noncoherent semaphore operators include the single and double versions of the following operations:

Fetch and Clear
Fetch and Increment
Fetch and Decrement

The fetch implies that the semaphore variable goes directly into a processor register. When either the fetch and increment or fetch and decrement instruction reads the variable, the EMAC automatically increments or decrements it.

In addition to these fetch instructions, noncoherent read and write operations are also available to access semaphore variables. If a noncoherent semaphore operator accesses a memory line that is encached by a processor, the semaphore operation will fail, resulting in an error being returned to the processor. All semaphore variables are 16-byte aligned. Semaphore operations to nonaligned variables produce undefined results.

Implementing noncoherent semaphore operations requires the following sequence of instructions using EPAC CSRs:

Check write access privilege for the semaphore address.
Arm the operation by writing to the EPAC Operation Context register Armed bit. See “EPAC Operation Context registers”.
Write the physical address to the EPAC Operation Address register.
Read the Fetch Operation address. The value read is the return value for the semaphore operation.
Check the EPAC Operation Context register Triggered bit to make sure the operation was issued. If the Triggered bit is not set, the operation must be restarted. The Armed bit is cleared when the sequence is interrupted by either an external interrupt or a TLB miss.
The other noncoherent semaphore operations and the noncoherent read operation can also use this sequence by using a different Fetch Operation CSR address. The noncoherent write operation is similar to the above sequence, except that the load instruction is replaced with a store instruction with the value to be stored.

As an example, the sequence of instructions for a fetch_and_inc32 is as follows:

      PROBEW  fetch_addr             ;Check protection
loop
      LDI     1,%t1
      STD     %t1,(CSR_OP_ARMED)     ;Arm CSR Operations
      LPA     fetch_addr,%t2
      STD     %t2,(CSR_OP_ADDR)      ;Fetch operation addr				
      LDW     CSR_FETCH_INC),%t3     ;Issue fetch semaphore				
      LDD     (CSR_OP_ARMED),%t4
      BB,*>=  %t4,62,loop            ;check if triggered

Noncoherent semaphore operators

Technical documentation

» Table of Contents

» Glossary