Not all threads in a multithread process complete at the same
time. All threads, however, must typically wait until the last thread
finishes. The threads hit a barrier and must be synchronized before
continuing.
The barrier synchronization semaphore is a running count of
the number of threads that have reached the barrier. The last processor
to finish writes a nonzero value to the semaphore address, signalling
to the other processors that the threads are synchronized.
An alternate method for barrier synchronization semaphore
operations requires a sequence of instructions using EPAC CSRs similar
to the sequence discussed in the section “Noncoherent semaphore operators”.
The following sequence of instructions provides an alternative
method for the coherent_inc64() function:
PROBEW cincd_addr ;Check protection
loop
LDI 1,%t1
STD %t1,(CSR_OP_CNTX) ;Arm CSR Operations
LPA cincd_addr,%t2
STD %t2,(CSR_CINCD) ;Issue Coh. Inc.
LDD (CSR_OP_CNTX),%t4
BB,*>= %t4,62,loop ;check if triggered
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The steps of the sequence are:
Check write protection for the operation
address.
Arm the operation by writing to the CSR Operation
Armed register Armed bit.
Perform virtual-to-physical address translation.
Fetch the Operation address. The value read is the
return value for the semaphore operation.
Check the EPAC Operation Context register Armed
bit to make sure the operation was issued. If the Triggered bit
is not set, then the operation must be restarted. The Armed bit
is cleared when the sequence is interrupted by either an external
interrupt or a TLB miss.
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