The EPAC has multiple registers and several addresses to implement
CSR-based semaphore operations. The two types of registers, the
Operations Context register and the Operation Address register,
are detailed in the chapter Chapter 4 “Data mover” The addresses are discussed in the following
sections.
EPAC Fetch Operation addresses |
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Each EPAC has six Fetch Operation addresses, three for each
processor pair. Reading these addresses triggers one of the following
noncoherent fetch semaphore operations:
If the Armed bit in the Operation Context register is set,
an access to one of the Fetch Operation addresses results in a fetch
operation to memory. When the Armed bit is set, the address contained
in the Fetch Operation Address register becomes the address for
the fetch operation. If the Armed bit is not set, the EPAC returns
the value zero to the processor rather than the data intended for
the fetch operation.
The size field determines whether the operation is word or
double word. Any word-aligned address can be used for word operations,
and any double-word-aligned address can be used for double-word
addresses.
EPAC Noncoherent Read and Write Operation addresses |
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Each EPAC has two Noncoherent Read Operation addresses, one
for each processor pair. Each EPAC also has two Noncoherent Write
Operation addresses, one for each processor pair. A read of the
noncoherent read address triggers the noncoherent read operation.
A write to a noncoherent write address triggers a noncoherent write
operation.
If the Armed bit in the Operation Context register is set,
the address contained in the Operation Address register becomes
the address for the operation. If the Armed bit is not set, the
EPAC returns the value zero to the processor rather than the data
intended for the noncoherent read operation. For a Noncoherent Write
Operation, if the Armed bit is not set, the EPAC drops the noncoherent
write.
The access size determines whether the operation is word or
double word. Any word-aligned address can be used for word operations,
and any double-word-aligned address can be used for double-word
addresses.
EPAC Coherent Increment addresses |
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Each EPAC has two Coherent Increment addresses, one for each
processor pair. Writes to these addresses trigger coherent increment
operations. If the armed bit in the Operation Context register is
set, the address contained in the Operation Address register becomes
the address for the fetch operation. If the Armed bit is not set,
then the EPAC ignores the write access.
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