Each PA-8200 TLB entry contains a bit that controls whether
an access to coherent memory space should accelerate the memory
line into its data cache. The V-Class server uses this bit to inhibit
noncoherent operations from being moved into data cache.
Table 5-1 “Semaphore
operation instructions” lists the supported
semaphore operators and the associated PA-8200 instructions used
to issue the operations for the accessed memory page.
Table 5-1 Semaphore
operation instructions
| TLB entry U-bit | PA-8200 instruction | Semaphore operation |
|---|
| 0 (Coherent) | LDCW | Load and Clear 32-bit |
| | LDCD | Load and Clear 64-bit |
| | CINCD | Coherent Increment 64-bit |
| | LDW | Noncoherent Load 32-bit |
| | LDD | Noncoherent Load 64-bit |
| | STW | Noncoherent Store 32-bit |
| | STD | Noncoherent Store 64-bit |
Mixing coherent and noncoherent accesses to a memory line
generates an error to the issuing processor.
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