Processor interrupts

System interrupts are applied to a processor by writing to its External Interrupt Request Register. The V-Class server interrupts occur from several sources which include:

The EIRR is written to using a double word store.

	NOTE: The fact that the EIRR can only be written to using double word stores is a deviation form the PA-RISC architecture. This is true of all processor CSRs.

All fields of the register are undefined when read.

The format of the EIRR is shown in Figure 6-1 “PA-8200 External Interrupt Request register definition”.

Figure 6-1 PA-8200 External Interrupt Request register definition

The Interrupt Number field (bits 26:31) specifies the external interrupt to be set in the EIRR. The value of the interrupt, 0-63, is encoded in the six-bit field.