Utilities board interrupts

Almost all interrupts are sent directly to the processor EIRR with the exception of those associated with the core logic bus connected to the Utilities board. The Utilities board collects system environmental interrupts and applies them to the EIRR. The Utilities board handles the following types of interrupts:

Environmental conditions
Transfer of control (TOC)
External communications
System warnings and failure

Figure 6-1 “PA-8200 External Interrupt Request register definition” shows how these interrupts are presented to the processor.

Figure 6-2 Core logic interrupt system

The Utilities board provides interrupt information to all EPACs in the system. Each EPAC determines if one of its two processors is enabled to handle the pending interrupt.

The Utilities board accepts eight separate interrupt sources listed in Table 6-1 “Core logic interrupt sources”.

Table 6-1 Core logic interrupt sources

Core logic interrupt source	Interrupt bit
DUART channel 0	0
DUART channel 1	1
SONIC controller	2
Transfer of control button	3
Transfer of control line (from test station)	4
Environmental warning	5
Environmental error	6
System hard error	7

The Utilities board processes interrupts as follows:

Interrupts are latched into the Interrupt Status register in the EMUC. Interrupts can also be forced into the Force Interrupts register for testing purposes (these are not masked).
Interrupts are compared to data in the Interrupt Mask register, and, if they are not masked out, are sent across the core logic bus to the Interrupt Delivery register in the EPAC.
If the EPAC determines that one of its processors has the interrupt enabled, it delivers the interrupt information to the processor by writing to the processor EIRR with the level of the interrupt in bits 26:31 of the 64-bit register, sending a Runway bus transaction to cause an HPMC or writing to the processor I/O Command register to cause a TOC.

EPAC interrupt logic

Each EPAC receives an eight-bit mask from the EPUC (using the core logic bus) that specifies the interrupt sources sent to the processors. Each EPAC has interrupt delivery information for each of the eight possible interrupt sources. Figure 6-3 “EPAC interrupt delivery information” shows the interrupt delivery data.

Figure 6-3 EPAC interrupt delivery information

The information contains individual enables for each of the two processors connected to an EPAC, the type of exception, and the interrupt number or an interrupt exception type.

Figure 6-4 “EPAC Interrupt Delivery register definition” shows where these bits are located in the EPAC Interrupt Delivery register.

EPAC Interrupt Delivery registers

There are two 64-bit Interrupt Delivery registers on each EPAC. Each register specifies the delivery information for four of the eight interrupt sources.

Figure 6-4 EPAC Interrupt Delivery register definition

The fields and bits of the EPAC interrupt delivery registers are defined as follows:

Processor enable bits—Indicate that the processor is enabled to handle the exception.

Exception type fields—Indicate the type of exception:

Interrupt
HPMC
TOC loss of synchronization
Power failure

Interrupt number fields—Indicate the interrupt source to the delivery registers.

The Utilities board interrupts map to the core logic interrupt delivery registers as shown in Table 6-2 “Core logic interrupt delivery registers”. All fields are written to by a CSR write and read using a CSR read. Reset has no effect on the register.

Table 6-2 Core logic interrupt delivery registers

Utilities board interrupt source	Register and bits
DUART channel 0	Register 0, bits 6:15
DUART channel 1	Register 0, bits 22:31
SONIC controller	Register 0, bits 38:47
Transfer of control button	Register 0, bits 54:63
Transfer of control line (from test station)	Register 1, bits 6:15
Environmental warning	Register 1, bits 22:31
Environmental error	Register 1, bits 38:47
System hard error	Register 1, bits 54:63

EPUC interrupt logic

The following EPUC interrupt registers comprise the EPUC interrupt logic:

Interrupt Status register
Interrupt Mask register
Interrupt Force register

EPUC Interrupt Status register

The EPUC contains one Interrupt Status register. The register maintains the status of the pending Utilities board interrupts given in Table 6-2 “Core logic interrupt delivery registers”. Figure 6-5 “EPUC Interrupt Status register definition” shows the definition of the register.

Figure 6-5 EPUC Interrupt Status register definition

The Interrupt source field (bits 0:7) indicates the source of the EPUC interrupt. The bits are set when the EPUC detects an active input interrupt signal. The contents of the register are read by a CSR read operation. Each bit set in the data of a CSR write operation clears the associated bit of the status register, and a reset clears the register.

Table 6-3 “EPUC Interrupt register field definitions” shows the bit field assigned to each core logic interrupt source.

Table 6-3 EPUC Interrupt register field definitions

Register bit	Interrupt source
0	DUART channel 0
1	DUART channel 1
2	SONIC controller
3	Transfer of control button
4	Transfer of control line (from test station)
5	Environmental warning
6	Environmental error
7	System hard error

Each individual bit of the Interrupt Status register can be cleared without affecting the other bits, even when the CSR is receiving an interrupt. For all bits except the transfer of control button, clearing a bit has precedence over setting it. This means that if an input interrupt is still asserted when the bit is cleared, the status bit is set on the following cycle, and a new interrupt is sent to each EPAC. The transfer of control button interrupt is edge-level sensitive, and the other interrupts are level sensitive.

EPUC Interrupt Mask register

The EPUC contains one Interrupt Mask register. The register enables sending the pending interrupts to the EPAC. It provides the ability to mask out any of the eight interrupt sources. Figure 6-6 “EPUC Interrupt Enable register definition” shows the definition of the register.

Figure 6-6 EPUC Interrupt Enable register definition

The Interrupt mask field (bits 0:7) indicates interrupts are masked. The contents of the register are read by a CSR read operation and written by a CSR write operation. A reset clears the register.

EPUC Interrupt Force register

The EPUC contains one Interrupt Force register. The register allows software to force an interrupt on any of the eight interrupts. Figure 6-7 “EPUC Interrupt Force register definition” shows the definition of the register.

Figure 6-7 EPUC Interrupt Force register definition

The Interrupt force field (bits 0:7) indicates the interrupt(s) being forced. The contents of the register are read by a CSR read operation and written by a CSR write operation. Setting a bit forces an interrupt, regardless if it is enabled of not. A reset clears the register. Table 6-3 “EPUC Interrupt register field definitions” shows the interrupts assigned to each core logic interrupt force bit.