The EPIC uses the concept of a logical I/O channel
to translate PCI addresses and prefetch system coherent memory.
A logical channel defines a pipe between four Mbytes of PCI memory
space to four Mbytes of system coherent memory.
Each channel has a distinct address mapping between the PCI
bus address space and the system main memory. It also has a buffer
for storing prefetched data during read data transfers. The buffer
hides PCI start-up latencies associated with read data transfers.
The logical I/O channel also has a posted write buffer
for collecting 32-byte data cache lines before flushing them to
system coherent memory. Figure 7-2 “Logical I/O channel model”
depicts the logical I/O channel concept, and Figure 7-3 “PCI bus command and address” shows the PCI bus command
and address format.
The 10 most significant bits of the PCI address define the
logical channel number, providing a total of 1,024 logical channels.
Channels 1008-1023 are reserved, leaving a maximum of 1,008 read
channels and 1,008 write channels. The 22-bit channel offset gives
each channel a four-Mbyte data space. Consecutive channels may be
chained to allow transfers larger than four Mbytes.
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 | NOTE: Each channel can be used for one or more DMA transfers
on a controller. Best performance is usually realized, however,
with a single I/O transfer per channel. A channel can not
be used by multiple controllers at the same time. |
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Channel initialization |
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Before a processor initializes an I/O operation,
it must set up a channel for the appropriate controller by writing
to the EPIC Channel Builder register.
The build consists of a single write to the Channel Builder
register. See the section “EPIC Channel Builder register”. The EPIC initializes all the external
SRAM channel context state and prefetches any needed data and TLB
entries.
Channel context and shared memory SRAM |
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The EPIC maintains both channel context and shared memory
in its external Channel Context SRAM (CCSRAM). The channel context
space reserves 64 Kbytes from the base of the SRAM, and shared memory
for both controller and expanded is available for the remainder.
The EPIC supports up from 256 Kbytes to 2 Mbytes of external CCSRAM.
See Figure 7-4 “CCSRAM Layout”.
The channel context portion of the SRAM contains information
to determine how to perform the DMA transfer between PCI and system
memory. Channel context is mapped into both PCI memory space and
processor I/O space. The channel context region, however,
is only directly accessed for diagnostic use. The processor programs
channel context state through the EPIC Channel Builder register.
The EPIC provides a locally shared memory region in the CCSRAM
for all status and control structures that support the PCI controllers.
This SRAM is not coherent with main memory. It is visible,
however, from both PCI memory space and processor I/O space.
Printable version
