The 40-bit system address map, shown in Figure 7-5 “I/O address space format”, reserves 16 Gbytes from F8 0000 0000
to FB FFFF FFFF for host access to PCI devices.
The fields for the I/O address space are defined
as follows:
Dxbr field bits
(6:9)—Specifies one of eight EPACs
Offset field bits (11:39)—Specifies
29-bit EPIC mapping.
PCI configuration space |
 |
The PCI specification establishes three PCI address spaces:
configuration, I/O, and memory. Dedicated read and write
commands select a particular space for a PCI bus operation.
The PCI configuration space contains a set of configuration
registers that must be implemented by all bus targets except host
bridges. The configuration registers allow the EPIC to set up PCI
I/O and memory space requirements in the system address
map. PCI configuration space is 16 Mbytes (24 bits). Figure 7-5 “I/O address space format” shows the PCI configuration
address format.
The fields for the I/O configuration space format
are defined as follows:
Bus number field
(bits 16:23)—Indicates PCI bus number. Bus 0 is the bus
directly attached to the EPIC. Any other PCI buses must be assigned
Bus numbers 1 to 255 during the software probe.
Device number field (bits 24:28)—Specifies
the device on one PCI bus segment. Bus 0 only supports Device 0
through Device 3.
Function number field (bits
29:31)—Specifies the function on a PCI device.
Register number field (bits
32:37)—Specifies the register within a PCI function.
Byte number field (bits 38:39)—Provides
the byte address. This field and the packet size code establish
the PCI byte enables during the access. Accesses must be aligned
to their natural size. The EPIC does not support 64-bit double-word
accesses to PCI.
PCI I/O and memory space |
|
PCI I/O and PCI memory space allow host access to
device-specific CSRs. Target implementation of either space is optional.
However, if a device implements either space, it must also implement
a corresponding base address register in PCI configuration space
to allow consistent address mapping.
PCI I/O and PCI memory space may each be as large
as four Gbytes. PCI I/O space uses a full byte address,
so the EPIC combines the least significant bits of the system address
with the packet size code to create the PCI byte address and the
PCI byte enables. PCI memory space uses four byte-aligned addresses;
smaller entities are addressed by bus byte enables.
I/O space-to-PCI map |
|
As shown in Figure 7-7 “I/O space to PCI space mapping”, the
EPIC maps its partition of I/O space into the three PCI
spaces. It also reserves an area for diagnostic windows into the
external EPIC context/shared memory and external EPIC prefetch
memory.
The PCI defines eight Gbytes of I/O and memory space,
but the EPIC only has 0.5 Gbyte of space in which to operate. Therefore,
the address map is necessarily sparse. Only the PCI configuration
space maps on a one-to-one basis.
The EPIC can generate PCI addresses, increasing from 0000
0000 in PCI I/O space and decreasing downward from FFBF
FFFF in PCI memory space. The allocation boundary between I/O
and memory space is programmable in 64-Mbyte increments and can
range from no I/O space and all memory space to no memory
space and all I/O space.
Maximizing the PCI I/O space also maximizes the number
of available PCI DMA channels, while increasing the PCI memory space
comes at the cost of 16 PCI DMA I/O channels per 64-Mbyte
increment.
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