Since most PCI controllers generate a 32-bit address, they
are capable of addressing up to four Gbytes. The V-Class server can
have more than this amount. Therefore, it provides for translating
the 32-bit addresses to system addresses. There are two types of
address translation: physical and logical. An Address Translation
Enable bit (ATE) for each channel determines the address translation
between PCI and system coherent memory.
In the physical translation mode, data is fetched directly
from a four-Mbyte buffer in system main memory.
Logical address translation implies that the translation process
uses an intermediate step to derive the system address. The process
uses translation tables in system memory for data transfers.
Most modern I/O controllers use part of the host
memory for storing control and status blocks. Typically, these are
accessed using word accesses over the PCI bus. Since the main memory
access latency is relatively large, part of the channel context
SRAM is used for storing the control and status structures.
By addressing logical channel 1023, a controller accesses
the entire SRAM.
Physical address translation |
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The simplest translation mode is the physical translation
mode. In this mode, the four-Mbyte PCI channel directly maps into
a four-Mbyte, physically contiguous block of system memory. The
22-bit PCI channel offset is combined directly with the 18-bit channel
physical base pointer to generate the 40-bit system address.
Some I/O transfers, specifically remote receive transfers
with many small I/O streams, need to be handled in a nondeterministic
order. If each transfer were located in its own channel, software
could run out of channels. If the transfers are packed into a single
logical channel, the TLB miss overhead when switching streams would
then limit the controllers throughput.
Software can pack remote receive buffers into a single physical
channel and reduce the number of channels used, reduce the number
of channel swaps, and eliminate TLB miss latencies.
Logical address translation |
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The more common way to map the 32-bit PCI address into the
40-bit system address is using a logical translation mode channel.
For logical translations, a translation table is used to generate
the 40-bit system address from the 32-bit PCI address.
The logical address translation mode is based on a translation
lookaside buffer much like the processor TLB. The translation table
converts the PCI bus addresses into system addresses on a page (four-Kbyte)
basis, and therefore, are aligned on page boundaries. A TLB base
pointer points to the page of TLB entries in system memory. The
PCI page number indexes this table, pointing to a system page number.
This system page number and the PCI page offset are combined to
generate the 40-bit system address.
The I/O TLB entries in system coherent memory are
the same as those used by the data mover. They are not the same
as the processor TLB entries.
An I/O page table consists of 1,024 TLB entries.
Each 28-bit TLB entry points to a four-Kbyte page of system coherent
memory. Therefore, the table consumes four Kbytes of system coherent
memory. The channel TLB base pointer points to its channel page
table. The PCI page number indexes the page table to address the
needed TLB entry. See Figure 7-9 “Logical mode address translation”.
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