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HP 9000 V-Class Server: Architecture > Chapter 7 I/O subsystem
PCI memory read transfers |
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To handle long and variant system memory latencies, the EPIC uses several different prefetch techniques in combination to ensure that the data needed by a controller is available at the time it is needed. These techniques include:
These techniques allow the EPIC to:
Read data is coherent at the point that the request is satisfied in system memory. I/O transfers are not included, however, in system memory sharing lists. Therefore, if the data is modified later, the EPIC prefetched data will be stale. This fact dictates that direct memory accesses (DMA) from system memory be used only for buffered data that is defined prior to the EPIC issuing any prefetches for that data. To purge prefetched data from the EPIC prefetch buffers, the channel must be either reinitialized or rebuilt through the Channel Builder register. To accommodate these prefetch techniques, the EPIC provides two types of data prefetch storage:
The channel prefetch space hides start-up latencies, and the device prefetch space maintains the streaming data. When a PCI transfer starts, data is supplied from the smaller channel prefetch buffer. Once that data from this buffer is exhausted, the data is pulled from the larger device prefetch buffer. Channel prefetch space stores channel prefetch data. This space hides the typical start-up latency for system accesses when a controller switches from one channel to another. There is one channel prefetch buffer per channel for a total of 1,008 channel prefetch buffers. The amount of storage space needed to cover the start-up latency for system accesses determines the depth of each channel prefetch buffer. The depth of the buffer is sized with the following formula: Channel prefetch depth = PCI bandwidth * Local memory latency Device prefetch space stores the prefetch data of a streaming device. It buffers a single controller stream of data from memory. The depth of the buffer is sized to hide latencies with minimal stalls on the PCI bus. There is one device prefetch buffer per controller. The depth of the buffer is sized with the following formula: Device prefetch depth = PCI bandwidth * Remote memory latency For small transfer high bandwidth controllers, the start up latency dictates the effectiveness of the controller to move data. The start up latency is the time from which a controller provides the EPIC a new address stream to the time the EPIC provides the first data word. The EPIC provides a Channel prefetch enable (P) bit to hide controller start-up memory latencies. When enabled (P is set to 1), the EPIC Channel Builder register prefetches data at channel initialization time. The prefetched data is stored locally in the channel space of the EPIC external SRAM. Therefore, when a controller presents the EPIC with an address mapping into this channel, the data is already local to the EPIC, reducing the latency to first data word. A controller that uses time-multiplexing on its read streams (for example, an ATM controller) can also be programmed with a Channel Refetch (R) bit. When this bit is enabled (R set to 1) and one channel is swapped for another, the EPIC first refetches data into the channel prefetch buffer, starting where the controller left off. This guarantees that when the controller comes back to this address stream, the next needed data is available in channel prefetch space. Each EPIC can be connected to controllers with different bandwidth requirements. The EPIC must ensure that each controller has fair access to the system memory. The EPIC consumption-based prefetch algorithm keeps the prefetch request rate matched to the amount of data that a controller is consuming from the EPIC. Each time a line of data is transferred across the PCI interface to a controller, a prefetch is scheduled for that EPIC device prefetch buffer. This also ensures that the depth of the prefetch buffer is maintained at the minimal level that satisfies the consumption rate of the controllers, keeping the EPIC from over prefetching for a particular controller. Occasionally a controller needs data that is not available in the EPIC device prefetch buffer (for example, when the controller address stream jumps outside the depth of the device prefetch buffer). In this case, the stall prefetch mechanism causes the EPIC to issue a constant stream of data prefetches at a programmable interval until the critical line returns to the EPIC. Once prefetch data is available, the prefetch algorithm reverts to the consumption-based prefetch algorithm. |
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