The EPIC has one independent write buffer per PCI controller.
In order to minimize the write traffic to memory, a write buffer
accumulates sequential bytes into a cache line of data prior to
sending it to system memory. Any of the following events can cause
the EPIC to flush this write buffer to memory:
The controller writes the last byte
of a cache line.
The controller writes a noncontiguous byte stream
(a jump).
A synchronization event forces a write pipe flush.
When the controller write buffer accumulates a cache line
of data, a WritePurge operation
flushes the line of data to memory. When the memory subsystem receives
the data, it purges this line from all processors.
When a partial line needs to be flushed to memory, however,
a WritePurge can not be used, since
the current cache line in memory must be merged with the partial
cache line of the EPIC. The EPIC provides a Write Purge Partial
(W) mode bit per channel that defines how the EPIC should perform
this partial cache line merging.
Write purge partial disabled |
 |
If the Write Purge Partial bit is cleared, the nonwritten
portion of the cache line in memory must be maintained coherently.
Therefore, the EPIC must perform a Dflush_Alloc/Write_Mask
flow. The EPIC first issues a Dflush_Alloc
to flush the line back to memory, locking down the line. When Dflush_Alloc
is complete, the EPIC issues the Write_Mask
operation. This operation writes the data to memory with a mask
to allow the memory subsystem to merge the two lines together and
release the line in memory.
Write_Purge_Partial enabled |
|
If the Write_Purge_Partial bit is set, there
is no guarantee that the nonwritten portion of the cache line in
memory is coherently maintained. Setting this bit provides accelerated
partial line transfers to system coherent memory, making this mode
suitable for transfers like those to kernel buffers but not suitable
for I/O transfers directly to user space.
The Write_Purge_Partial provides a mask
that defines the data to be written to memory. The remaining bytes
of the cache line come from what is currently in memory. When this
data is received, the memory subsystem purges any users of the cache
line.
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