The EPIC is controlled by CSRs. All CSRs are 64-bit aligned
and may only be accessed using noncoherent Read Short and Write
Short packets. The EPIC registers include:
EPIC CSR address decoding |
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The EPIC CSR address decoder looks at system address bits
[4:5] to determine the target address space (I/O
or EPIC CSRs) and bits [24:39] to index the CSR
space. Accesses to unimplemented EPIC CSR space return error responses
to the requestor. Reserved addresses and bits ignore writes and
return zeros on reads.
The EPIC CSRs may be accessed by addressing, the mapping of
which is shown in Figure 7-11 “EPIC CSR 40-bit address format”.
The bits and fields of the EPIC CSR space address are as follows:
DXbr field (bits
18:19)—Specifies which of the eight cross bar ports the
request is to be routed.
Chip field (bits 21:23)—Routes
the packet to the appropriate chip at a crossbar port.
Page field (bits 28:36)—Separates
groups of CSRs into similar usage spaces.
EPIC CSR definition |
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This section describes the EPIC CSRs.
EPIC Chip Configuration register
The EPIC contains one EPIC Chip Configuration register on
each EPIC. It specifies configuration information.
The fields of the EPIC Chip Configuration register are defined
as follows:
EPIC part number
field (bits 0:15)—Specifies the part number for the EPIC
chip. A write is ignored and a read returns the hardwired value.
EPIC version code field (bits
16:19)—Specifies the version of the EPIC chip. A write
is ignored and a read returns the hardware value.
Implementation dependent field
(bits 20:63)—Specifies implementation dependent information.
The value in this field should not be modified during normal use.
PCI Master Configuration register
There is one PCI Master Configuration register on each EPIC
that provides configuration information about the PCI Master interface.
The format of the register is shown in Figure 7-13 “PCI Master Configuration register
definition”. All reserved fields are read as zero,
and writes are ignored. All implemented fields are read with the
last value written.
The fields and bits in the EPIC PCI Master Configuration register
are defined as follows:
Arbitration disable timeout
field (bits 0:15)—Defines the PCI arbitration disable timeout
threshold.
Reset PCI bus field (bit 23)—Resets
the PCI bus.
PCI memory I/O boundary field
(bits 29:31)—Controls the amount of I/O space
mapped to PCI MEM and PCI I/O address space in contiguous
64-Mbyte blocks.
PCI memory space limit field
(bits 38:47)—Resets to 0x3f0 or 1008 decimal. The EPIC
reserves the upper 60-Mbytes (channels 1008-1022 inclusive) for
PCI controller shared memory address space and the highest four
Mbytes (channel 1023) for EPIC context SRAM. The EPIC does not respond
to PCI Controller DMA from channels 1,022 down to the value stored
in this register. This register value updates on write to the PCI
Memory_I/O Boundary field, and is read-only.
Disable PCI retry counter bit
(bit 50)—Specifies the PCI retry counter is enabled.
Enable data byte swap during host access
to PCI bit (bit 51)—Causes host accesses to
the PCI to swap data bytes.
Disable Host highest priority
bit (bit 54)—Indicates the host is participating in rotating
priority with other devices.
Disable PCI bus arbiter timeout on bus
grants bit (bit 55)—Indicates that the PCI bus
arbiter does not timeout on bus grants.
Master Parity Error Response
bit (bit 59)—Indicates that the EPIC performs its normal
operation when it detects a parity error as bus master.
Generate bad address parity on PCI master
writes bit (bit 62)—Forces bad address parity
out to PCI (for diagnostic use only).
Generate bad data parity on PCI master
writes bit (bit 63)—Forces bad data parity out
to PCI (for diagnostic use only).
PCI Master Status register
Each EPIC has one PCI Master Status register that provides
status information for the PCI Master interface. All fields are
cleared by a reset except the EPIC Device Select Timing field; it
is hardwired to the value one.
The bits in the EPIC PCI Master Status register are defined
as follows:
PCI bus in reset
bit (bit 0)—Indicates that the PCI bus is reset.
Parity error detected bit (bit
3)—Indicates that the EPIC detected a parity error on incoming
read data while the EPIC was bus master.
Data parity error detected
bit (bit 7)—Indicates that a parity error was detected
on the bus while EPIC was PCI bus master.
Sent master abort bit (bit
8)—Indicates that the EPIC was master and sent a Master
Abort (no target claimed the bus cycle). The Host receives an error
response.
Saw target abort bit (bit 11)—Indicates
that the EPIC was master and received a Target Abort. The Host will
receive an error response.
Broken device bit (bit 12)—Indicates
that the EPIC PCI interface received a grant and an Idle bus for
16 clocks but did not run a bus cycle. The EPIC returns an error
response to the requestor and sets the Master error in the Error
Cause register.
EPIC device select timing field
(bits 14:15)—Sets medium-speed address decode on PCI. This
field is read-only.
EPIC Channel Builder register
The EPIC Channel Builder register on each EPIC sets up channel
context in preparation for an I/O operation. The format
of the register is shown in Figure 7-15 “EPIC Channel Builder register definition”.
Writing to this register stores the value to all fields, and reading
it returns the last written value. A reset clears all fields. A
read from the Channel Builder register returns the current state.
A write to the Channel Builder register causes channel state to
be modified as defined by the written data.
The fields and bits in the EPIC Channel Builder register are
defined as follows:
Operation code
field (bits 0:1)—Determines the operation the channel builder
will perform.
Write channel field (bit 3)—Indicates
a memory write channel when set or a memory read channel when cleared.
Controller PCI slot number
field (bits 4:5)—Determines the PCI slot that this channel
uses.
Channel number field (bits
6:15)—Indicates the PCI channel to be built. The valid
range is from 0 to the PCI memory space limit.
Page number field (bits 16:25)—Indicates
the 10-bit PCI page number.
Line number field (bits 26:31)—Indicates
the line number inside the page from which to start prefetch (only
applies if a read channel, i.e. the Write Channel bit =
0).
A - Address translation enable
bit (bit 32)—Indicates the channel is in logical mode (translation
on), if the A bit is set to a one value. If the A bit is set to
a zero value, the channel is in physical mode (address translation
off). This field also interprets the translation table base Pointer
field.
T -TLB fetch enable bit (bit
33)—If set, TLBs are fetched from memory; if T=0,
only previously encached TLBs are available.
P -Prefetch/Write purge partial enable
bit (bit 34)—Indicates that data prefetch starts at the
same time as channel build for read channels. It indicates that
write purge partials are enabled for a write channel.
R -Refetch bit (bit 35)—Enables
data refetch prior to a read channel being swapped out.
Translation table entry/Physical base
pointer field (bits 36:63)—Indicates EPIC function
as follows:
If the A bit is set to a one value
and operation code is either a Build
or Init, then the field is the
translation table base pointer. This 28-bit field points to the
translation table base address where TLBs are fetched.
If the A bit is set to a one value and operation
code is a Prefetch, this field
is the 28-bit TLE for the data prefetch.
If the A bit is set to a zero value the field is
an 18-bit physical base pointer for this channel number, pointing
to a four-Mbyte physically contiguous block of memory.
EPIC Interrupt Configuration register
The EPIC has one EPIC Interrupt Configuration register that
specifies the interrupt number and processor when an interrupt occurs.
The EPIC forwards the interrupt by writing the interrupt number
to a local processor EIRR register. Since the EPIC can only send
interrupts to one of the 16 processor EIRR registers on the system,
only four bits of the address are programmable. All programmable
fields are reset to zero.
The fields and bits in the EPIC Interrupt Configuration register
are defined as follows:
Destination crossbar port
field (bits 18:20)—Indicates the crossbar port (and therefore
which EPAC) to which the interrupt will be sent.
Even/Odd processor chip field
(bits 23)—Specifies which of the two processors for the
given EPAC the interrupt is to be sent.
Interrupt number (bits 58:63)—Indicates
the processor External Interrupt register interrupt bit to be set.
EPIC Interrupt Source register
Each EPIC has one Interrupt Source register that holds pending
EPIC interrupts. Source bits are set when the source of the interrupt
occurs and remains set until cleared. Interrupts are accumulated
regardless of the state of the enable. If the interrupt is enabled
in the EPIC Interrupt Enable register, then EPIC sends an interrupt.
If the interrupt enable is written to a one value while the interrupt
is pending in the Interrupt Source register, the EPIC generates
an interrupt following the response to the register write.
The bits in the EPIC Interrupt Source register are defines
as follows:
EPIC soft error
bit (bit 15)—Indicates that a bit has been set in the Error
Cause register that is configured as a soft error.
Saw SERR_ field (bit 31)—Indicates
the EPIC received an SERR_ on the PCI bus.
EPIC Interrupt Enable register
EPIC Interrupt Enable register has a bit for every source
interrupt in EPIC Interrupt Source. A one value in any EPIC Interrupt
Enable bit causes an interrupt when the corresponding source event
in EPIC Interrupt Source occurs. This register resets to zero (all
interrupts disabled). The format for this register is shown in Figure 7-18 “EPIC Interrupt Enable register definition”.
The bits in the EPIC Interrupt Enable register are defined
as follows:
EPIC soft error enable
field (bit 15)—Indicates that an interrupt can be sent
when a soft error occurs. A value of one enables the interrupt.
SERR_ Interrupt Enable field
(bit 31)—Indicates that an interrupt can be sent when a
PCI SERR_ occurs.
PCI Slot Configuration register
There are four PCI Slot Configuration registers, one for each
supported PCI expansion slot. These registers provide control of
the PCI interface.
The bits in the PCI Slot Configuration register are defined
as follows:
PCIx interrupt synchronization
disable bit (bit 19)—Disables the synchronization
of a device on interrupt.
PCIx interrupt enable bit (bit
23)—Enables the forwarding of a device interrupt.
PCIx Perr response bit (bit
39)—Enables PCI_PERR_ data parity error
signalling.
PCIx_Swap SRAM bit (bit 46)—Enables
byte swapping on PCIx shared memory transfers.
PCIx_Swap DMA bit (bit 47)—Enables
byte swapping on PCIx DMA transfers.
PCIx Arb Disable bit (bit 55)—Disables
bus arbitration for PCIx.
PCIx Read Manager Reset bit
(bit 58)—Resets EPIC Read manager x.
PCIx Write Manager Reset bit
(bit 59)—Resets EPIC Write manager x.
Each EPIC has four PCI Slot Status registers that specify
the status of slot specific events. Bits in these registers are
set when EPIC is the target of one of the four controllers and a
status event occurs. All writable fields are reset to the value
zero.
The fields and bits in the PCI Slot Status register are defined
as follows:
PCIx interrupt line
bit (bit 3)—Indicates the current state of the PCIx INTA_
line (read only).
PCIx sent target abort bit
(bit 7)—Indicates that the EPIC sent this slot a Target
Abort bus cycle termination. This bit does not set the PCI Controller
x bit in the Error Cause register.
Saw address parity error bit
(bit 11)—Indicates that the EPIC detected an address phase
parity error on a transfer from this slot. The EPIC terminates the
transfer with target abort and relies on the transaction master
to report the error to software. This bit sets the PCI Controller
x bit in the Error Cause register.
Broken device bit (bit 12)—Indicates
this slot received a grant during an idle bus for 16 clocks but
did not run a bus cycle.
Saw data parity error bit (bit
15)—Indicates the EPIC (as a target) detected a PCI data
phase parity error on incoming (write) data from this slot. This
bit does not set the PCI Controller x
bit in the Error Cause register.
PCI card present/power requirements code
field (bits 30:31)—Indicates a PCI controller is present
and the power requirements of that controller. This field is read
only.
PCI Slot Interrupt Configuration register
Each EPIC has four PCI Slot Interrupt Configuration registers
that specify the interrupt number and processor when an interrupt
occurs on the corresponding PCI slot. The EPIC forwards the interrupt
by writing the interrupt number to a local processor EIRR register.
Because the EPIC can only send interrupts to one of the 16 processor
EIRR registers on the system, only four bits of the address are
programmable. All programmable fields are reset to zero.
The fields in the EPIC PCI Slot Interrupt Configuration register
are defined as follows:
Destination crossbar port
field (bits 18:20)—Determines to which crossbar port (and
therefore which EPAC) the interrupt will be sent.
Even/Odd processor chip field
(bits 23)—Specifies which of the two processors for the
given EPAC the interrupt is to be sent.
Interrupt number field (bits
58:63)—Specifies the processor External Interrupt register
interrupt bit to be set.
PCI Slot Synchronization register
The EPIC has four PCI Slot Synchronization registers, one
for each of the four PCI bus slots. Software polls these registers
to determine when the write pipe has been flushed.
A processor reads these registers to synchronize the write
pipe for the corresponding device. The registers are read-only,
and the CSR interface returns zero status after the requested device
operation completes. The format of the PCI Slot Synchronization
register is shown in Figure 7-22 “PCI Slot Synchronization register
definition”.
The Synchronization status bit (bit 55)
specifies the completion status of the device write manager for
the corresponding slot.
Printable version
