Byte swapping

In order to address different byte ordering between the PCI bus and the rest of the system, the EPIC provides CSR-configurable bits to define how to handle byte ordering of data crossing from one domain into the other. The CSRs configure byte swapping on the following data paths:

PCI read and write of system coherent memory on a per-controller basis via the PCI Slot Configuration register (see the section “PCI Slot Configuration register”)
PCI read and write of shared memory on a per-controller basis via the PCI Slot Configuration register
Host read and write of PCI I/O, Memory, and Configuration space via the PCI Master Configuration register (see the section “PCI Master Configuration register”)

Byte swapping

Technical documentation

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