This section describes the core logic bus and core logic hardware
functions.
Flash memory |
 |
The core logic contains nonvolatile storage for processor-dependent
code. This code consists of primary loader code, the Open Boot PROM
(OBP) code, the OBP interface firmware, spp_pdc,
and power-on self test software (POST) (see the chapter Chapter 10 “Booting and testing” for more information).
This EEPROM memory is four MBytes, configured as one-million addresses
by 32 data bits with only 32-bit read and write accesses allowed.
It is writable by the processors for field upgrades and can be written
when the EPUC is scanned.
Nonvolatile static RAM |
|
The core logic section contains a nonvolatile battery-backed
static RAM (NVSRAM). The NVSRAM is used to write system log information
(failures) and store configuration information. This RAM is byte
addressable and can be accessed even after power failures occur.
DUART |
|
The ECUB logic contains a Dual Universal Asynchronous Receiver-Transmitter
(DUART). One port, configured as a basic RS232 port, provides an
interface to the simplest core system functions. With this interface,
you can connect a terminal as a local console to analyze problems,
reconfigure the system, or provide other user access. The parallel
port of the DUART drives the LCD. The second RS232 port can be connected
to a modem for field service.
RAM |
|
RAM is needed to support the simple core system functions.
When the system powers up, the processors operate out of this RAM.
They run self test software to test and configure the rest of the
system. Once the system is fully configured, the processors execute
out of main memory. The RAM is byte addressable and is 128 KBytes,
configured as 32K addresses by 32 data bits (with parity).
Console ethernet |
|
The ethernet I/O port connects to another optional
system console that has an ethernet port. You can use the console
for initializing, testing, and troubleshooting the system.
LEDs and LCD |
|
LEDs display environmental information, such as the source
of an environmental error that caused the ECUB to power down the
system.
The LCD is driven by one of the processors via the ECUB. A
large amount of information can be displayed on the LCD. The core
logic drives the LCD via the parallel port on the DUART.
COP interface |
|
COP chips (serial EEPROMs) are located on the major boards
with information such as serial number, error history, configuration
information, and so on. The EMUC connects to the COP bus selector
(CBS) chip on the ENRB and allows the system to read any COP in
the system.
Printable version
