The EPUC applies interrupts and error messages to the processors
and receives control messages from the processors. It has two 18-bit,
bidirectional buses. Each interface connects up to four EPACs. The
EPUC provides core logic bus arbitration for the sixteen processors.
Through the EPUC, the EPAC has an interface to the core logic
bus on the ECUB. This bus connects the EPUC, the EMUC, and the core
logic section together.
EPUC Processor Agent Exist register |
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The Processor Agent Exist register indicates which EPACs exist
in the system. During reset, all EPACs assert their REQ lines. This
sets corresponding bits in this register. The EPUC ignores the REQ
lines (with respect to core logic bus requests) approximately eight
clocks after reset to allow the EPACs to change from exist
mode to request mode.
A value of one on any bit indicates that the respective EPAC
0-7 is active and exists.
EPUC Revision register |
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The Revision register indicates the revision level of the
EPUC FPGA.
Revision bits are read to determine the revision of the EPAC.
Printable version
