The JTAG interface supports a teststation and a mechanism
to fan out JTAG to all the boards in a system. It is used only for
testing.
The JTAG functions are described in the following sections.
Teststation interface |
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The teststation can be a PA-RISC based workstation. The interface
to the teststation is an ethernet AUI port for flexibility in connecting
to many workstations.
AC test |
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An ac test is performed by a Test Bus Controller (TBC) scanning
in data to all boards in the system and loading an ac test instruction
into all ASICs on one board.
Once all boards have been almost loaded with the ac test instruction
and paused, the TBC takes all boards out of pause mode simultaneously
causing them all to exit update together and execute the ac test.
The ac test enables clocks inside the ASICs so that they test
internal and external paths at the system clock rate. They all execute
on the same system clock.
Clock margining |
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Parallel ports on the core logic microprocessor select the
nominal, upper, or external clock that drives the system.
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