Testing

The system uses LAN1 for testing, running diagnostics on the system, and reconfiguring the system manually. All diagnostic accesses to memory occur through CSR space. A 64-bit register holds eight bytes for writing and reading memory. The memory transfer size is 64 bits. The diagnostic operations are:

Memory line data read
Memory line data write
Memory line initialization
Memory read ECC
Memory write ECC
Memory line scrub

Diagnostic memory read Operations

A diagnostic memory read is performed by writing to the memory line address of the Diagnostic Address CSR on the EMAC. The EMAC interprets the write to the CSR address as a request to read the data at the addressed memory line. The 64-bit data is read from the SDRAM memory and written to the EMAC diagnostic data register. The processor requesting the memory read can then access the data with a 64-bit CSR access. Figure 10-3 “CSR memory read operation” illustrates the flow for a CSR memory read operation.

Figure 10-3 CSR memory read operation

Diagnostic memory write operations

A diagnostic memory write operation uses the same CSRs as the read. The data is written to the CSR data register, and the address at which the data is to be stored is written to the CSR diagnostic address register.

EMAC diagnostic CSRs and addresses

This section defines some of the EMAC CSRs that perform the diagnostic memory operations.

EMAC Diagnostic Address register

There is one Diagnostic Address register on each EMAC that supplies the address for diagnostic memory accesses.

The format of the Diagnostic Address register is shown in Figure 10-4 “EMAC Diagnostic Address register definition”.

Figure 10-4 EMAC Diagnostic Address register definition

The Row field (bits 30:32), Memory bank field (bits 36:37), Page field (bits 38:51), Page offset field (bits 52:58), and Longword field (bits 59:60) together specify the memory address for diagnostic accesses.

The Longword bit is used for diagnostic memory data reads and writes where a specific eight-byte longword must be accessed.

Bank interleaving is not performed by the EMAC; the processor must perform the mapping from the virtual bank to the memory bank.

All fields are written by a CSR write and read by a CSR read. A Diagnostic Memory Initialization operation increments the concatenated Page and Page Offset fields as part of the operation.

EMAC Diagnostic Data register

The Diagnostic Data register holds eight bytes of data used for diagnostic memory reads and writes. The format of the Diagnostic Data register is shown in Figure 10-5 “EMAC Diagnostic Data register definition”.

Figure 10-5 EMAC Diagnostic Data register definition

EMAC Diagnostic Read Memory Data address

Writing to the EMAC Diagnostic Read Memory Data address obtains eight bytes of data from the address specified by the Diagnostic Address register. The Diagnostic Address register is not modified by this operation.

EMAC Diagnostic Write Memory Data address

Writing to the EMAC Diagnostic Write Memory Data address moves eight bytes of data to the address specified by the Diagnostic Address register. The operation is similar to the read memory data operation, except that the Diagnostic Address register also specifies which of the four eight-byte longwords of a 32-byte line is to be written with the data in the Diagnostic Data register. Neither the Diagnostic Address nor Diagnostic Data register is modified by the operation. ECC is regenerated for the entire memory line by this operation.

EMAC Diagnostic Memory Read ECC address

The data in the memory line is stored in four consecutive SDRAM locations. Each SDRAM location is protected with an eight-bit ECC. Writing to the EMAC Diagnostic Memory Read address triggers a memory read operation of the ECC associated with the address specified in the Diagnostic Address register. The Longword field of the Diagnostic Address register specifies which ECC (of the four SDRAM locations) is to be read. The accessed ECC is written to the eight least significant bits of the Diagnostic Data register. The Diagnostic Address register is not modified by the operation.

EMAC Diagnostic Memory Write ECC address

Writing to the Diagnostic Memory Write ECC address triggers a memory write operation of the ECC associated with the address specified in the Diagnostic Address register. The Longword field of the Diagnostic Address register specifies which of the four SDRAM locations the ECC is to be written. The SDRAM ECC is written with the least significant eight bits of the Diagnostic Data register.

EMAC Diagnostic Memory Initialization address

Writing to the EMAC Diagnostic Memory Initialization address triggers a memory write operation to the tag and data of a memory line. The address of the memory line is specified by the Diagnostic Address register. The memory tag is written with the contents of the Diagnostic Data register, and the 32 bytes of memory data associated with the memory line are written with the value zero. The Diagnostic Data register is not modified. The concatenated Page and Page Offset fields of the Diagnostic Address register are incremented to address the next sequential memory line. The Longword field of the Diagnostic Address register is ignored.

EMAC Diagnostic Scrub Memory address

Writing to the EMAC Diagnostic Scrub Memory address triggers a read and write to the memory line at the address specified by the Diagnostic Address register. If a single bit ECC error occurs when the data is read, the data is corrected before it is written back into memory. If no ECC error occurs, the data is written back unmodified.