Glossary

An address that does not undergo virtual-to-physical address translation when used to reference memory or the
I/O register area.

A number used by the operating system to identify a storage location.

Memory space, either physical or virtual, available to a process.

Errors that are usually corrected by hardware or firmware

The physical structure of a computer"s internal operations, including its registers, memory, instruction set, and I/O structure.

A control mechanism used in parallel programming that ensures all processors have completed the prior operation before continuing with the next operation.

A group of data containing a fixed number of bytes.

A type of TLB entry that translates many contiguous virtual pages to an equal number of contiguous physical pages.

The procedure by which a program is initiated the first time. Typically, a bootstrap is performed when power is first applied to the processor.

A temporary storage area. Several types of buffers are used in computer systems, in both hardware and software. The most common types of buffers are those maintained by a computer operating system to mediate between processes and I/O devices.

A data path shared by several components within a computer system.

See cache memory.

A small, high-speed buffer memory used in modern computer systems to hold temporarily those portions of the contents of the main memory that are, or believed to be, currently in use.

A type of interruption caused by the detection of an internal hardware detected malfunction.

A term frequently applied to caches. If a data item is referenced by a particular processor on a multi-processor system, the data is copied into that processor cache and is updated there if the processor modifies the data. The state that is achieved when both processors' caches always have the latest value for the data is called cache coherency.

See Hyperplane crossbar

Control and status register. A software-addressable hardware register used to hold control or state information.

Hardware that routes messages and copies data between memory.

A procedure or method defined for gaining direct access to main storage and achieving data transfers without involving the processor.

See direct memory access.

Exemplar Core Utilities board. Located on the ENRB, the ECUB provides system booting and testing functions.It connects to the core logic bus, the system environmental sensors, and other test points, as well as the optional teststation.

See electrically erasable programmable read-only memory.

A read-only memory module that can be programmed repeatedly by first erasing the previous contents of the memory module. Unlike the EPROM, the EEPROM can be reprogrammed without removal from the circuit board by applying an erase signal to the device.

Exemplar Memory Access Controller. The gate array that controls system memory. It interfaces to the routing array controller (ERAC) Each EMAC controls four banks of memory, allowing up to 32 banks in an eight-EMAC system.

Exemplar Processor agent controller. The gate array that interfaces to pairs of PA-RISC processors.

Exemplar PCI Interface Controller. The heart of the S-Class and X-Class I/O subsystem. The EPIC connects to the PCI bus and provides and interface between I/O devices and the EPAC.

Exemplar Routing Array Controller. The ASIC (four required) used to in the system Hyperplane crossbar. The crossbar provides an interface between the processors and I/O devices and system memory.

The status returned by a function call.

Code used to decide which bit of a memory read operation is in error.

A hardware-detected event that disrupts the running of a program, process, or system. See also fault.

A type of interrupt caused by an instruction that requests a legitimate action that cannot be carried out immediately due to a system problem.

An uncorrectable data error.

High priority machine check. Indicates that a process error occurred and that the process cannot continue. The system requires rebooting after an HPMC.

A switching device used in multiprocessor, shared-memory computer systems that connects processors to the various banks of memory in the system.

Memory used to hold frequently accessed instructions.

A physical path between any two modules or systems.

Memory that is divided into multiple banks to permit concurrent memory accesses. The number of separate memory banks is referred to as the memory interleave. Programs can optimize memory accesses by using stride intervals so that each of the banks can be refreshed between memory accesses.

An occurrence that changes the normal flow of instruction execution. An interrupt originates from hardware, such as an I/O device. See also maskable interrupt.

An interval timer is used to generate an interrupt based on the passage of time.

Joint Test Action Group. Formerly a group of European and later American companies that developed a boundary scan technique to facilitate in-circuit testing and functionality testing of circuit boards. It was handed off to the IEEE and refined as IEEE Standard 1149.1.

The time delay between the issuing of an instruction and the completion of the operation. A common metric used for comparing parallel processor systems is the latency of coherent memory.

Low priority machine check.It is similar to a processor trap in that it is not fatal to a process.

See physical memory.

An interrupt to which the operating system may choose not to respond.

A type of programming in which program modules (often running on different processors or different hosts) communicate with each other by means of system library calls that package, transmit, and receive data.

The operation of bringing information from memory into a cache.

A complete system that consists of a set of up to 16 processors and up to 64 Gbytes of physical memory organized as a symmetric multiprocessor (SMP) running a single image of the operating system microkernel.

A memory reference that 1) does not cause a cache move-in, or 2) causes a cache move-in, but fails to obey cache coherency rules.

The Hewlett-Packard precision architecture reduced instruction set computer. A RISC instruction set is easy to decode in hardware and for which a compiler can generate highly optimized code.

A group of related items. A packet may refer to the arguments of a subroutine or to a group of bytes that is transmitted over a network.

The unit of logical memory controlled by the memory management algorithms. A page in the V-Class server is 4 Kbytes (4,096) contiguous bytes.

Unit of physical (main) memory in which pages are placed. Referenced and modified bits associated with each page frame aid in memory management.

Physical page directory. PA-RISC processors that implement hardware TLB miss handlers may fetch TLB entries from a PDIR entry in the event of a TLB miss. The PDIR serves as a cache of virtual-to-physical page translations and is maintained by the operating system.

A unique identifier that selects a particular device from the set of all devices connected to a particular bus.

The set of possible addresses for a particular bus.

Memory devices, usually RAM, connected as a subsystem that provide fast-access storage for the operating system, applications, and data.

The fundamental unit of a program that is managed by the job scheduler. A collection of one or more execution streams within a single logical address space; an executable program. A process is made up of one or more threads.

A hardware entity that contains an address, operand, or instruction status information.

The process of establishing a known state in a machine register.

The data interface of the Hewlett-Packard PA-8200 processor. It allows multiprocessor systems to interface to memory and I/O without additional components.

Synchronous Dynamic Random Access Memory.

A group of bits associated with data structures that act as a flag to all processors to synchronize the threads of a multiple-thread process. See also synchronization.

A process that fulfills a request issued by a client process, and transmits a response back to the client.

A memory architecture in memory can be accessed by all processors in the system. This architecture can also support virtual memory. This type of memory is sometimes referred to as shared virtual memory or global virtual memory.

Single Inline Memory Module.

Externally flushing or invalidating a cache line from a processor cache. The flushing or invalidating transaction is issued by the processor agent and is referred to as a "snoopy transaction." This action occurs when one processor in the system loads or stores to a dirty line in the cache of another processor, or when a processor stores to a line that is shared by one or more processors in the system.

Correctable single-bit memory error. May further be defined as transient (non-reproducible) or stuck (reproducible).

A contiguous range of virtual addresses within the system wide virtual address space.

A way to keep two threads from accessing the same critical region simultaneously. You can synchronize programs using compiler directives, thread library calls, or assembly-language instructions. You do so, however, at the cost of additional overhead; synchronization may cause at least one processor to wait for another.

The terminal or workstation that serves as a communication device between the system manager and the computer system. On the V-Class server, the teststation serves as the system console.

The workstation that is used to diagnose problems and install system software.

An independent execution stream that is fetched and executed by a processor. One or more threads, each of which can execute on a different processor, make up each process. Threads are created and terminated by instructions that can be automatically generated by compilers, inserted by adding compiler directives to source code, or coded explicitly in Fortran, C, or C++ programs.

Data that is accessible by a single thread only (not shared among the threads constituting a process). Thread-specific data allows the same virtual address to refer to different physical memory locations.

Translation Lookaside Buffer. A hardware structure in each processor of the V-Class server that contains the information necessary to translate a virtual memory reference to a physical page and to validate memory accesses.

Time of Century. Used register to time stamp trace data and interprocess messages.

A type of interrupt caused when either the function requested by the current instruction cannot or should not be carried out, or system intervention is desired by the user before or after the current instruction is executed. Typically, this condition is a result of unexpected arithmetic results.

An address used by a program to access data or instructions. The V-Class server maps each virtual address to physical memory location.

Two different virtual addresses that map to the same physical memory address.

The time an application requires to complete its processing. If an application starts running at 1:00 p.m. and finishes at 5:00 a.m. the following morning, its wall-clock time is sixteen hours.

The term that applies to virtual-to-physical address translation indicating that the two addresses remain the same after translation.