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Architecture: HP 9000 V-Class Server

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HP Part Number: A3725-96022

Second Edition

March, 1998

Revision History
Revision First	A3725-96004
Initial release October, 1997.
Revision Second	A3725-96022
Released March, 1998.

Table of Contents

New in Second Edition
System platforms
Notational conventions

1 Introduction

The PA-8200 processor

Control and status registers (CSRs)
Description of functional blocks

System configurations

Shared memory

2 Physical address space

Physical addresses

Coherent memory space

Coherent memory layout
Addressing a byte of memory
Memory interleaving
Memory interleave generation

Core logic space

Local I/O space

Non-I/O CSR space

Processor-local access
EPAC-local access
System accesses
Access to nonexistent CSRs
System Configuration register
EPAC Configuration register
EPAC Processor Configuration register
EPAC Memory Board Configuration register
EMAC Configuration register
EMAC Memory Row Configuration register

Processor caches

Cache coherence between processors

Accelerated cache coherence

Address aliasing

Equivalent aliasing
Nonequivalent aliasing
Instruction aliasing

4 Data mover

Message transfers
Data copy
Data mover features

Data mover implementation

Functional overview
Messaging and data copy CSRs
Memory structures

5 Synchronization

Coherent semaphore instructions

Noncoherent semaphore operators

Barrier synchronization

EPAC semaphore addresses

PACFOA EPAC Fetch Operation addresses
EPAC Noncoherent Read and Write Operation addresses
EPAC Coherent Increment addresses

PA-8200 TLB Entry U-bit

6 Interrupts

Processor interrupts

Utilities board interrupts

EPAC interrupt logic
EPUC interrupt logic

7 I/O subsystem

Logical I/O channel

Channel initialization
Channel context and shared memory SRAM

Host-to-PCI address translation

PCI configuration space
PCI I/O and memory space
I/O space-to-PCI map

PCI-to-host memory address translation

Physical address translation
Logical address translation

PCI memory read transfers

Channel prefetch space
Device prefetch space
Channel prefetch/refetch modes
Device consumption-based prefetch
Stall prefetch

PCI memory write transfers

Write purge partial disabled
Write_Purge_Partial enabled

I/O subsystem CSRs

EPIC CSR address decoding
EPIC CSR definition

Byte swapping

8 Performance monitors

Performance factors

Performance monitor hardware

Interval timer
Time-of-Century clock
Performance monitoring counters

9 System utilities

Utilities board

Flash memory
Nonvolatile static RAM
DUART
RAM
Console ethernet
LEDs and LCD
COP interface

EPUC Processor Agent Exist register
EPUC Revision register

EMUC and Power-on

Environmental monitoring functions
Monitored environmental conditions
Environmental control
EMUC CSRs

JTAG interface

Teststation interface
AC test
Clock margining

10 Booting and testing

Teststation-to-system communications

LAN 0 communications
LAN 1 communications
Serial communications

Hardware reset
Power-On Self Test routine
HP-UX bootup

Diagnostic memory read Operations
Diagnostic memory write operations
EMAC diagnostic CSRs and addresses

11 Error handling

Soft errors
Advisory errors
Hard errors
Error responses
Error handling CSRs
Processor error detection
EPAC error detection
ERAC error detection
EMAC error detection

List of Figures

1-1 Functional block diagram of a V-Class system
1-2 ERAC interconnection
2-1 Physical address space partitioning
2-2 Coherent memory space address formats
2-3 Coherent memory space layout
2-4 Conceptual layout of physical memory of a fully populated system
2-5 40-bit coherent memory address generation
2-6 Single memory block interleave pattern
2-7 Memory line interleave pattern with four memory blocks
2-8 40-bit core logic space format
2-9 Core logic address translation
2-10 40-bit local I/O space format
2-11 Non-I/O CSR space format
2-12 System Configuration register definition
2-13 EPAC Configuration register definition
2-14 EPAC Processor Configuration register definition
2-15 EPAC Memory Board Configuration register definition
2-16 EMAC Configuration register definition
2-17 Memory Row Configuration register definition
4-1 Messaging and data copy transfers implementation
4-2 EPAC CSR Operation Context register definition
4-3 EPAC Operation Address register definition
4-4 EPAC Input Command register format
4-5 EPAC Physical Page Frame register definition
4-6 EPAC Source and Destination Offset register definition
4-7 Operation Status Queue register definition
4-8 EMAC Message Reception Area Configuration register definition
4-9 EMAC Message Reception Area Offset register definition
4-10 EMAC Message Completion Queue Configuration register definition
4-11 EMAC Message Completion Queue Offset register definition
4-12 EMAC Message Completion Enqueue definition
4-13 EMAC Message Completion Dequeue definition
4-14 Message Completion Queue and entry definition
4-15 Block Translation Table and Entry definition
6-1 PA-8200 External Interrupt Request register definition
6-2 Core logic interrupt system
6-3 EPAC interrupt delivery information
6-4 EPAC Interrupt Delivery register definition
6-5 EPUC Interrupt Status register definition
6-6 EPUC Interrupt Enable register definition
6-7 EPUC Interrupt Force register definition
7-1 I/O system block diagram
7-2 Logical I/O channel model
7-3 PCI bus command and address
7-4 CCSRAM Layout
7-5 I/O address space format
7-6 I/O PCI configuration space format
7-7 I/O space to PCI space mapping
7-8 Physical mode address translation
7-9 Logical mode address translation
7-10 I/O TLB entry format
7-11 EPIC CSR 40-bit address format
7-12 EPIC Chip Configuration register definition
7-13 PCI Master Configuration register definition
7-14 PCI Master Status register definition
7-15 EPIC Channel Builder register definition
7-16 EPIC Interrupt Configuration register definition
7-17 EPIC Interrupt Source register definition
7-18 EPIC Interrupt Enable register definition
7-19 PCI Slot Configuration register definition
7-20 PCI Slot Status register definition
7-21 PCI Slot Interrupt Configuration register definition
7-22 PCI Slot Synchronization register definition
8-1 EPAC TIME_TOC Configuration register definition
8-2 TIME_TOC Clock register definition
8-3 EPAC Performance Monitor Latency register definition
8-4 EPAC Performance Monitor Memory Access Count Pn register definition
9-1 Utilities board
9-2 EPUC Processor Agent Exist register definition
9-3 EPUC Revision register
9-4 Processor Report register definition
9-5 Processor Semaphore register definition
9-6 ERAC Data register definition
9-7 ERAC Configuration Control register definition
9-8 EMUC Reset register definition
10-1 teststation-to-system communications
10-2 POST program flow
10-3 CSR memory read operation
10-4 EMAC Diagnostic Address register definition
10-5 EMAC Diagnostic Data register definition
11-1 Determining error types
11-2 SADD_LOG after error response
11-3 EPAC error response information when received from either crossbar input

List of Tables

1-1 System configurations
2-1 Bank/ring index selection
2-2 Memory block interleave pattern for one pair
2-3 Memory block interleave pattern for two pairs
2-4 Memory block interleave pattern for four pairs
2-5 Memory bank interleave pattern for four banks
2-6 Core logic space partitions
2-7 Field specifications for system access
4-1 CSR Operation Context register transitions when the operation is issued
4-2 CSR Operation Context register transitions with TLB invalidate
4-3 Completion status field values
4-4 Error code values
4-5 Message Reception Area size options
4-6 Offset bits used for each size option
4-7 Message Completion Status field values
4-8 Message Completion Status field values
4-9 Message Completion Status field values
5-1 Semaphore operation instructions
6-1 Core logic interrupt sources
6-2 Core logic interrupt delivery registers
6-3 EPUC Interrupt register field definitions
8-1 TIME_TOC resolutions
9-1 Environmental conditions monitored by the EMUC and power-on circuit
9-2 Environmental LED display
9-3 Reset register read codes
9-4 Reset register write codes
11-1 SADD_LOG error source field definition
A-1 V-Class server CSR map

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