The cell board with its firmware is the biggest change to
the Superdome family. It provides the processing and memory resources
required by each Superdome system configuration. Each cell board
uses up to four Itanium® 2 processor modules Superdome)
or up to four PA-8800, dual-core, PA-RISC processor modules (hp 9000 Superdome), a
single cell (or coherency) controller (CC), a high-speed crossbar interface,
a high-speed I/O interface, eight memory controller CCs, capacity
for up to 32 high-density DIMMs, high-speed clock-distribution circuitry,
a utility subsystem interface, scan (JTAG) circuitry for manufacturing test,
and a low-voltage DC power interface. The system backplane accommodates
up to eight cell boards allowing up to 32 processor modules and
up to 256 DIMMs in a single system cabinet.
The cell power board (OCPB) is separate from the cell board.
An OCPB can attach to any cell board.
The heart of the cell board, the coherency controller (CC),
provides a Front Side Bus (FSB) interface to each of two processor
module pairs. The communication bandwidth (6.4 GB/s at 200 MHz)
of both FSB interfaces on the CC is, therefore, split between two
processor modules. Interfaces external to the cell board provided
by the CC constitute a crossbar interface, referred to as the fabric,
and a remote I/O subsystem link. The fabric interface allows multiple
cell boards to communicate with each other across a self-correcting,
high-speed (8 GB/s) communication pathway. The remote I/O link provides
a self-correcting, high-speed (2 GB/s) communication pathway between
the cell board and the I/O subsystem through a pair of cables. In
addition, the CC also provides the cell board with its own interface
to the cell board’s local memory subsystem.
Cell Controller |
 |
The CC has five major interfaces:
Processor (two independent FSBs)
Crossbar (cell interconnect fabric)
Platform-dependant hardware (PDH)
Using an internal, centralized data path, the CC maintains
cache coherency throughout the system with memory tags. It also
has an internal PLL that helps simplify clock distribution within
the confines of the ASIC and source additional clocks to the memory
and PDH subsystems.
Processors
and Front-Side Bus Interfaces |
|
Each of the two FSBs is connected to two processor modules
in a standard three-drop FSB configuration. The CC minimizes total
routing delay without sacrificing timing skew between the FSB address
and data and control signals to achieve a frequency of 200 MHz transmitting
data on both edges of the interface clock. With the 128-bit FSB
capable of achieving 400 MT/s, a 6.4 MB/s burst data transfer rate
can be realized.
Crossbar
Link |
|
The crossbar link is a self-correcting, high-speed interface
between the CC and the crossbar backplane. It comprises eight data “bundles,” each
with a differential strobe for synchronization, designed to achieve
a peak data transfer rate of 2 GB/s. Four of the eight bundles are
used for input data, and each bundle contains either 18 or 19 bits.
The other four bundles are used for output data and are also either
18 or 19 bits in width. The crossbar link has a built-in link presence
detect capability that effectively prevents either the CC or the crossbar
from driving signals into an unpowered device on the opposite side
of the link.
Remote
I/O Link |
|
The remote I/O link is a self-correcting, high-speed interface
that connects between the CC and the SBA through a pair of differential
cables. This differential link has one input differential data “bundle” and
one output differential data “bundle,” each with
a differential strobe for synchronization. The link achieves a peak data
transfer rate of 1 GB/s. Embedded inside each of the cables is a
differential signal pair that sends utility subsystem information
through the cables from a core I/O card plugged in to the remote
I/O Backplane. This utility information allows for the diagnosis
of various cable interconnect problems that might be encountered during
system installation, maintenance, or normal operation. The differential
link has a built-in presence detect capability that effectively
prevents either the CC or SBA/LBA from driving signals into an unpowered device
on the opposite side of the link.
Memory
Interface—Memory Multiplexer |
|
The memory interface of the Memory Multiplexer (MM—shown
in Figure 1-6 “Cell Board Functional Block Diagram” as JAB) multiplexes
and demultiplexes data between the CC and the SDRAM in the memory
subsystem. The data portion of the memory subsystem enters and exits
the CC on four 72-bit wide Memory Interface Data (MID) buses, each
bus running at 500 MT/s. The MID bus provides an independent access
path to memory, with its own address bus, control bus, data bus,
the MMs, and DIMMs. Only the data and TAG portions of the memory
subsystem are routed through the MM devices. All address and control
signals to the DIMMs are generated by the CC and are sent directly
to the DIMMs by way of memory interface address and control buses.
This results in lower memory latency.
Processor
Dependent Hardware |
|
The PDH uses an Intel 80C251 embedded micro controller and
a USB interface chip to provide hardware resources required for
both system and utility firmware. The utility subsystem employs
an intelligent interface that is capable of passing multiple forms
of information between system firmware and the MP by way of the
PDHC.
Features provided by the PDH hardware include:
512 KB Flash EPROM for PDHC boot-strap
code storage
512 KB PDHC SRAM for operational instruction and
data storage
Disposal CPLD provides memory-mapped Cars to control
the cell board for multiple utility subsystem needs
System Management Bus (Snubs) for reading of the
processor EEPROM, scratch EEPROM, and thermal sensing device
I2C Bus for reading
PDH, cell board, and cell power board FRU identification information
Control and monitoring of cell board local power
Timing control of cell board reset signals
Logic analyzer port for accessing PDH signals
Arbitration between the processors (system firmware)
and the utility subsystem to allow the utility subsystem access
to PDH peripheral components, which include:
12-MB FLASH EPROM for system firmware
boot-strap code storage
1-MB system firmware scratch pad SRAM for operation
instruction and data storage
512-KB battery backed Non-Volatile RAM (NVRAM)
Wall-clock information provided by a battery-backed
real-time clock (RTC) chip
Marshal FPGA provides memory-mapped registers for
configuration-related information
Serial Presence Detect (SPD) bus for detection and
investigation of loaded DIMMs
Low-level debug and general purpose debug port (UART)
Cell Power
Board |
|
The Cell Power Board (OCPB) attaches to the cell board and
provides redundant 12v, 3.3v, and 1.5v power for the (cell board.
There is one OCPB per cell board. It contains 8 DC-DC converters,
a linear regulator, input protection and filter components, in-rush
current limiting circuitry, five LED indicators, and various status and
control logic devices. The OCPB is not hot swappable by itself.
Printable version
