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Site Preparation Guidehp Integrity Superdome andhp 9000 Superdome > Appendix B Configuration Guidelines
Configuration Guidelines |
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To achieve the best performance and high availability consider the following factors as shown in order of importance: Each cell has two memory busses that must be evenly populated to achieve full bandwidth and reduce latency. Configurations of 4 Gbytes, 8 Gbytes, 12 Gbytes, 16 Gbytes, and 32 GBytes per cell accomplish this. Memory must be symmetric within each partition for interleaving to be even across all the cells, otherwise performance problems can result. Consider the following example: Example B-1 Incorrect Memory Distribution Across Partitions If a two cell partition has 2 Gbytes of memory on one cell and 16 Gbytes on another, 4 Gbytes will be interleaved (two from each cell) and 14 Gbytes will be assigned to one cell only. This will result in inconsistent bandwidth and latency problems. A group of four cells (a quad) resides on one Crossbar Chip (XBC) and has the lowest latency. Quads are slots 0-3, 4-7, 8-11 and 12-15. Keep partitions with a size less than or equal to four on the same quad. Memory traffic from one quad to another is routed in pairs. The following pairs share the same path: 0 and 1, 2 and 3, 4 and 5, and 6 and 7. The Superdome SD32 or hp 9000 Superdome SD32 can have dual links between quads if U-turns are installed on the backplane. To use both links a six-cell partition uses slots 0-3, 5, and 7 as would 4 and 6. Partitions that share links share common points of failure. XBC-XBC links can saturate and kill performance. An eight-cell partition on an SD6400 should be spread across cabinets. Cab 0, slots 0-3, 5, 7 and Cab 1, slots 4 and 6. For best performance, partitions should be either single cell or greater powers of 2: 2, 4, 8, and 16 cells. Memory interleaving is performed by taking either four or six physical address bits and using them to index into a cell mapping table entry consisting of 16 or 64 sub-entries. For a single cell partition, each sub-entry is loaded with only one cell. A two-cell partition alternates between the two cells. There is one 64 sub-entry cell map entry and a 48-16 sub-entry cell entry. Partitions that are not powers of two will undergo revisiting. Consecutive accesses will go through all the cell boards and come back through revisiting as many cells as necessary until all memory is utilized and the 64-entry table is filled. Table 1, SD64 Partition Configurations, shows configurations that yield the best performance. However, memory may be left over. This memory is interleaved in the 16-entry tables and does not always yield the best performance. Depending on the memory configuration and the partition size the memory system performance will always increase, although not always linearly. Use the following guidelines when building partitions:
The partitions in the following table provide good but not always optimum link loading while allowing for growth. Table B-1 SD64 Partition Configurations
Table 2 and Figure B-1 “SD64 ” show the SD64 partition configurations. Table B-2 SD64 Partition Configurations
A simple calculation can be made to evaluate whether or not a particular configuration will have bottlenecks.
The lower the link load, the better off the system. If link loads begin to approach 2, bottlenecks may occur. For a dual cabinet system, there are six equations covering each link:
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