 |
» |
|
|
|
The HP Integrity rx7620 Server is a 10U, 8-socket Symmetric Multi-Processing,
rack-mount server that accommodates up to 64 GB of memory, PCI-X
I/O, and internal peripherals, including disks and DVD/tape. Its high
availability features include N+1 hot-pluggable fans and power,
redundant power cords, and hot-pluggable PCI-X cards and internal
disks. It currently accommodates up to 8 IA64 processor modules with
a maximum of four processor modules per cell board and a maximum
of two cell boards. System
Backplane | |
The system backplane comprises the system clock generation
logic, the system reset generation logic, DC-to-DC converters, power
monitor logic, and two Local Bus Adapter (LBA) link-to-PCI converter
ASICs. It also includes connectors for attaching the cell boards,
the PCI-X backplane, MP/SCSI Core I/O boards, SCSI cables, bulk
power, chassis fans, the front panel display, intrusion switches,
and the system scan card. Unlike Superdome or the rp8400, there
are no Crossbar Chips (XBC) on the system backplane. The “crossbar-less” back-to-back
CC connection increases performance and reduces costs. Only half of the MP/SCSI Core I/O board set connects to the
system backplane. The MP/SCSI boards plug into the backplane, while
the LAN/SCSI boards plug into the PCI-X backplane. System
Backplane to PCI-X Backplane ConnectivityThe PCI-X backplane uses two connectors for the SBA link bus
and two connectors for the high speed data signals and the manageability
signals. SBA link bus signals are routed through the system backplane
to the cell controller on each corresponding cell board. The high speed data signals are routed from the SBA chips
on the PCI-X backplane to the two LBA PCI bus controllers on the
system backplane. The system backplane contains reset and clock circuitry that
propagates through the whole system. The central clocks drive all
major chip set clocks. Therefore, these circuits represent a system
wide single point of failure. I/O Subsystem | |
The cell board to the PCI-X board path runs from the CC to
the SBA, from the SBA to the ropes, from the ropes to the LBA, and
from the LBA to the PCI slots seen in Figure 1-4 “PCI-X Board to Cell Board Block Diagram”. The CC on cell board 0 and cell board 1 communicates
with one each SBA over the SBA link. The SBA link consists of both
an inbound and an outbound link with an effective bandwidth of approximately
1 GB/sec. The SBA converts the SBA link protocol into “ropes.” A
rope is defined as a high speed point to point data bus. The SBA
can support up to 16 of these high-speed bi-directional rope links
for a total aggregate bandwidth of approximately 4 GB/sec. Each LBA
acts as a bus bridge, supporting either one or two ropes and capable
of driving 33 Mhz or 66 Mhz for PCI cards. The LBAs can also drive
at 66 Mhz or 133 Mhz for PCI-X cards. | | | |  | NOTE: PCI-X slots 1-7 are dual rope slots while slot 8 is
a single rope slot. A rope is defined as a high speed point to point
data bus. | | | | |
The PCI-X backplane is the primary I/O interface for HP Integrity rx7620 Server systems.
It provides sixteen 64-bit, hot-plug PCI/PCI-X slots. Fourteen of
the slots have dual ropes connected to the LBA chips. The remaining
two slots have a single rope connected to each LBA chip. Each of
the sixteen slots are capable of 66MHz/33MHz PCI or 133MHz/66MHz
PCI-X. All sixteen PCI slots are keyed for 3.3 volt connectors (accepting
both Universal and 3.3 V cards). The PCI-X backplane does not provide
any 5 volt slots for the I/O cards. See Table 1-1 “PCI-X Slot Types” for more details. The PCI-X backplane is physically one board but behaves like
two independent partitions. SBA 0 and its associated LBAs and eight
PCI-X slots form one I/0 partition. SBA 1 and its associated LBAs
and eight PCI-X slots form the other I/0 partition. One I/O partition
can be powered down separately from the other I/O partition. Table 1-1 PCI-X Slot Types | I/O Partition | Slot | Device[1] |
|---|
0 | 8 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 7 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 6 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 5 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 4 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 3 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 2 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 0 | 1 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 8 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 7 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 6 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 5 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 4 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 3 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 2 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. | 1 | 1 | PCI (33 or 66 MHz) / PCI-X (66 or 133
MHz) 64-bit, 3.3V connector, Hot Plug Slot. |
|
Printable version
