The Frame Buffer

Physical Address Space

The physical frame buffer is addressed as 2048x1024 bytes. The last 768 bytes of each line of the address space (those to the right of the screen) are not displayed and no memory exists in those areas.

Figure 4-1 Physical Address Space

The medium resolution displays are addressed the same as above except that the display memory is only 1024x768 pixels.

To Access the Frame Buffer Directly

When using the R_GET_FRAME_BUFFER gescape for direct user access to the frame buffer, correct access can only be assured by using the R_LOCK_DEVICE and R_UNLOCK_DEVICE gescapes.

	CAUTION: Do not read from or write to the offscreen addresses. Such operations will cause unexpected errors.

Frame Buffer Address Mapping

The frame buffer is organized as a single one-dimensional array of pixel values. The first byte (byte 0) of the frame buffer represents the upper left corner pixel of the screen. Byte 1 is immediately to its right. Byte 1279 is the last (right-most) displayable pixel on the top line. The next 768 bytes are not displayable. Byte 2048 is the first (left-most) pixel on the second line from the top. The last (lower right corner) pixel on the screen is byte number 2,096,383 (1023x2048+1279).

Figure 4-2 Frame Buffer Mapping in Memory

The frame buffer organization is essentially the same for all the devices except for the number of banks. The integrated graphics systems (HP 705/710/715/725) have one bank of 8 planes. The GRX, CRX and Dual CRX have two banks of 8 planes (one for each buffer), and the CRX-24 and CRX-24Z have three banks of 8 planes (one for each color). Only one bank can be accessed at a time. Use the bank_switch call to select a bank to read or write. For information on bank_switch, read the section "Changes to bank_switch()" in Chapter 1.

For block_read and block_write operations to the image planes, the data is in all eight bits of each byte. The Z-buffer for the CRX-24Z is 24-bits deep. For the integrated graphics systems color, CRX, Dual CRX or CRX-24 with PowerShade, the Z-buffer is 16-bits deep. The default for reading the Z-buffer is always 32-bits per pixel. The Z-buffer data is shifted to be either leftmost 24 or 16 bits within the 32-bit word. The raw parameter to block_read and block_write must be set to true in order to read or write to the Z-buffer. Using bank 3 in the bank_switch command on the CRX-24 and CRX-24Z, or bank 2 on the other displays, selects the Z-buffer for reads or writes.

Unlike the frame buffer, the Z-buffer data is contiguous. The CRX-24Z Z-buffer is always 1280x1024 and word 1280 is the leftmost word of the second scanline. For either the integrated graphics systems color, CRX, Dual CRX or CRX-24, the Z-buffer is the size of the window. For example, if the window is 400x400, word 400 is the leftmost Z-buffer value for the second scan line.

Frame Buffer Configurations

The following table shows which color map modes are supported for different frame buffer configurations. No entry (i.e. blank) indicates no support.

Since Starbase supports double-buffering per window, it is better to request double-buffering with a depth of eight on the GRX, CRX, Dual CRX, and CRX-24, or a depth of 12 when in CMAP_FULL mode on CRX-24. Double-buffering with less than 8 planes (4/4, 3/3, 2/2, 1/1) is supported for compatibility with previous devices, however, it is not recommended. The write_enable and display_enable masks are used to accomplish double-buffering with less than 8 planes. Flashing may occur, however, as this kind of double-buffering cannot be done on a per window basis.