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The level 1 optimization modules are: Faster register allocation.
The examples in this section are shown at the source code
level wherever possible. Transformations that cannot be shown at
the source level are shown in assembly language. See Table 4-4 “Descriptions of Assembly Language Instructions ” for descriptions of the assembly
language instructions used. Branch
Optimization | |
The branch optimization module traverses the procedure and
transforms branch instruction sequences into more efficient sequences
where possible. Examples of possible transformations are: Deleting branches whose target is
the fall-through instruction; that is, the target is two instructions
away. When the target of a branch is an unconditional
branch, changing the target of the first branch to be the target
of the second unconditional branch. Transforming an unconditional branch at the bottom
of a loop, branching to a conditional branch at the top of the loop,
into a conditional branch at the bottom of the loop. Changing an unconditional branch to the exit of
a procedure into an exit sequence where possible. Changing conditional or unconditional branch instructions
that branch over a single instruction into a conditional nullification
in the following instruction. Looking for conditional branches over unconditional
branches, where the sense of the first branch could be inverted
and the second branch deleted. These result from null then clauses and from then clauses that only contain goto statements. For example, the code:
if(a) {
.
.
.
statement 1
} else {
goto L1;
}
statement 2
L1: becomes: if(!a) {
goto L1;
}
statement 1
statement 2
L1: Dead
Code Elimination | |
The dead code elimination module removes unreachable code
that is never executed. For example, the code: if(0) {
a = 1;
} else {
a = 2; becomes: a = 2; Faster
Register Allocation | |
The faster register allocation module, used with unoptimized
code, analyzes register use faster than the coloring register allocator
(a level 2 module). This module performs the following: Inserts entry and exit code. Generates code for operations such as multiplication
and division. Eliminates unnecessary copy instructions. Allocates actual registers to the dummy registers
in instructions.
Instruction
Scheduler | |
The instruction scheduler module performs the following: Reorders the instructions in a basic
block to improve memory pipelining. For example, where possible,
a load instruction is separated from the use of the loaded register. Where possible, follows a branch instruction with
an instruction that can be executed as the branch occurs. Schedules floating-point instructions.
For example, the code: LDW -52(0,30),r1
ADDI 3,r1,r31 ;interlock with load of r1
LDI 10,r19 becomes: LDW -52(0,sp),r1
LDI 10,r19e
ADDI 3,r1,r31 ;use of r1 is now separated from load Table 4-4 Descriptions of Assembly Language Instructions Instruction | Description |
|---|
LDW offset(sr, base), target | Loads a word from memory into register target. | ADDI const, reg, target | Adds the constant const to
the contents of register reg and puts the result
in register target. | LDI const, target | Loads the constant const into
register target. | LDO const(reg),target | Adds the constant const to
the contents of register reg and puts the result
in register target. | AND reg1, reg2, target | Performs a bitwise AND of the contents
of registers reg1 and reg2 and puts
the result in register target. | COMIB cond const, reg, lab | Compares the constant const to
the contents of register reg and branches to
label lab if the condition cond is true. | BB cond reg,num,lab | Tests the bit number num in
the contents of register reg and branches to
label lab if the condition cond is true. | COPY reg, target | Copies the contents of register reg to register target. | STW reg, offset(sr, base) | Store the word in register reg to memory. |
Peephole
Optimizations | |
The peephole optimization process involves looking at small
windows of machine code for optimization opportunities. Wherever
possible, the peephole optimizer replaces assembly language instruction
sequences with faster (usually shorter) sequences, and removes redundant
register loads and stores. For example, the code: LDI 32,r3
AND r1,r3,r2
COMIB,= 0,r2,L1 becomes: BB,>= r1, 26, L1 |
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