Glossary

One of the basic operations defined by the IEEE standard.

The type of address that a data object has in memory. Data objects can have 1-byte, 2-byte, 4-byte, or 8-byte alignment, meaning that the object is stored at an address evenly divisible by 1, 2, 4, or 8.

A collection of object modules. When an application is linked with an archive library, the linker scans the contents of the archive library and extracts the object modules that satisfy any unresolved references in the application. The linker copies the archive library modules into the application's code section. See also shared library.

A version of a comparison assertion that treats a NaN (Not-a-Number) as a special value that compares as neither less than nor greater than any normalized value, and as unequal to any value, including another NaN and itself. See also non-aware.

In a floating-point representation, a value that is subtracted from the represented exponent to get the actual exponent. For single-precision formats, the bias is 127; for double-precision formats, it is 1023; for quad-precision formats, it is 16383. See also biased representation.

A ­floating-point representation that adds a constant value (the bias) to the actual exponent, so that actual exponents, which may be negative or positive, are always represented as positive.

The Basic Linear Algebra Subroutine (BLAS) library, a math library that contains routines that perform low-level vector and matrix (array) operations. This library is provided with the HP Fortran 90 and FORTRAN/9000 products only.

Two sets of data or instruction addresses that have the same n low-order bits and therefore occupy the same cache address. See also data cache aliasing, instruction cache aliasing.

The ceiling of a value is the smallest whole number greater than that value. See also floor.

One of the basic operations defined by the IEEE standard. The comparison operation determines the truth of an assertion about the relationship of two floating-point values. There are four possible relations: less than, equal, greater than, and unordered. See also aware, non-aware.

A compile-time expression evaluation that determines whether an expression evaluates to a constant and, if it does, replaces the expression with the constant.

See floating-point status register.

One of the basic operations defined by the IEEE standard.

The form of cache aliasing that occurs when the addresses of two data objects have the same low-order bits but different high-order bits. See also cache aliases, instruction cache aliasing.

A floating-point value that is represented by a sign bit, a zero exponent, and a non-zero fraction. (If the fraction were also zero, the floating-point value would be zero.) A denormalized value has a magnitude greater than zero and less than any normalized value.

One of the basic operations defined by the IEEE standard.

The exception condition that occurs when the system attempts to divide a nonzero, finite value by zero; more generally, when an exact infinity is produced from finite operands.

Errors generated by math library routines when they encounter invalid arguments. See also range errors.

See quad-precision.

An IEEE floating-point format in which a value occupies 64 bits: 1 bit for the sign, 11 bits for the exponent, and 52 bits for the fraction. See also single-precision, quad-precision.

See exception condition.

See exception condition.

A condition that may require special handling to make further execution of an application meaningful. In many applications, the occurrence of an exception indicates an error. The IEEE standard specifies five exception conditions: the inexact result condition, the overflow condition, the underflow condition, the invalid operation condition, and the division by zero condition. See also trap handler.

A group of bits in the floating-point status register. If an exception condition occurs and the corresponding exception trap enable bit is not set, the floating-point unit (FPU) sets the corresponding exception flag to 1, but does not cause a trap.

A group of bits in the floating-point status register. If an exception condition occurs and the corresponding exception trap enable bit is set, the floating-point unit (FPU) causes a trap. When the enable bit equals 0, the exception usually sets the corresponding exception flag to 1 instead of causing a trap.

In a floating-point representation, the bits that represent a value to which 2.0 is raised. See also fraction, sign bit.

See flush-to-zero mode.

See flush-to-zero mode.

A representable floating-point value (that is, not an infinity or a NaN (Not-a-Number)).

Of or pertaining to the method by which computer systems represent and operate on real numbers. The IEEE standard specifies that a floating-point value consists of a sign bit, a fraction, and an exponent.

A register in the floating-point unit (FPU) on PA systems that controls the arithmetic rounding mode, controls the underflow mode (on many systems), enables user-level traps, indicates exceptions that have occurred, indicates the result of a comparison, and contains information to identify the implementation of the floating-point unit.

A coprocessor that performs IEEE floating-point operations on PA-RISC systems. Also called the floating-point coprocessor.

The floor of a value is the greatest whole number less than that value. See also ceiling.

On some systems, a method of handling underflow conditions in which the hardware simply substitutes a zero for the result of an operation that underflows, with no fault occurring. (Normally, an underflow involves a fault into the kernel, where the IEEE-754-specified conversion of the result into a denormalized value or zero is accomplished by software emulation.)

Fused Multiply-Add, a kind of instruction that combines a multiplication and an addition into a single operation. Also called FMAC (floating-point multiply accumulate).

In a floating-point representation, the bits that for normalized values represent a value between 1.0 and 2.0 that is raised to a power of 2. See also exponent, sign bit.

In a ­floating-point representation, the bit in the fraction that would represent 1.0. Since this bit would always be set, it is not included in the actual format, but it is implied.

See fraction implicit bit.

The IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985), which defines specifications for representing and manipulating floating-point values so that programs written on one IEEE-conforming machine can be moved to another conforming machine with predictable results. The international version of the IEEE standard is Binary floating-point arithmetic for microprocessor systems (IEC 559:1989).

Of or pertaining to a computation in which small changes to the input or to the intermediate results cause relatively large changes in the final output.

The exception condition that occurs when a ­floating-point operation produces a result that cannot be represented exactly in the specified floating-point format. Because most floating-point operations produce inexact results most of the time, the inexact result condition is not usually considered to be an error. See also rounding.

A floating-point value that is represented by a sign bit, a fraction that is all zeros, and an exponent that is all ones. An infinity has a magnitude greater than any normalized value.

The form of cache aliasing that occurs when two routines reside at addresses that have the same low-order bits but different high-order bits. See also cache aliases, data cache aliasing.

The exception condition that occurs whenever the system attempts to perform an operation that has no numerically meaningful interpretation (for example, 0.0/0.0).

In double-precision and quad-precision floating-point formats, the 32-bit word in the representation that contains the last portion of the fraction. See also most significant word.

A collection of commonly used routines, pre-compiled in object format and ready to be linked to an application.

See exception trap enable bits.

A library that contains routines that perform higher-level mathematical operations. On HP 9000 systems, C math library functions are located in the libm math library; Fortran and Pascal intrinsic functions are located in the libcl library; and Basic Linear Algebra Subroutine (BLAS) library routines are located in the BLAS library (libblas).

In double-precision and quad-precision floating-point formats, the 32-bit word in the representation that contains the sign bit, the exponent field, and the first part of the fraction. See also least significant word.

One of the basic operations defined by the IEEE standard.

A floating-point value that is represented by a sign bit, a fraction with at least one bit set to 1, and an exponent with all bits set to 1. See also signaling NaN (SNaN), quiet NaN (QNaN).

The alignment that corresponds to the length of the object. For example, the natural alignment of an HP C int is 4-byte alignment.

A version of a comparison assertion that behaves the same as the aware version, except that if either or both operands is a quiet NaN (QNaN), it also signals an invalid operation condition for the <, <=, >, and >= assertions. See also aware.

See normalized value.

See fraction implicit bit.

A floating-point value that is represented by a sign bit, a fraction, and an exponent whose bits are not all zeros and not all ones. A normalized value has a magnitude greater than any denormalized value and less than infinity.

See ill-conditioned.

See invalid operation condition.

See invalid operation condition.

The exception condition that occurs when a ­floating-point operation attempts to produce a result whose magnitude, after rounding, is greater than the maximum representable value.

The sections of code that require the most execution time.

The process of refining a program to make it run faster.

The number of bits or digits in which a value can be represented. The precision of a value indicates how close a floating-point approximation can be to the exact numeric value being represented.

See quiet NaN (QNaN).

The HP-UX implementation of the IEEE double-extended precision floating-point format, in which a value occupies 128 bits: 1 bit for the sign, 15 bits for the exponent, and 112 bits for the fraction. See also single-precision, double-precision.

A NaN (Not-a-Number) that usually does not generate an exception; instead, it silently propagates unmodified through an operation. On HP 9000 systems, a QNaN has the most significant bit of the fraction set to 0. See also signaling NaN (SNaN).

Errors generated by math library routines when they underflow or overflow. See also domain errors.

One of the basic operations defined by the IEEE standard.

The default IEEE rounding mode, which specifies that the result of an operation should be the representable value closest to the true value. If two representable values are equally close to the true value, the result is the one whose least significant bit is 0 (that is, whose last digit is even).

One of the basic operations defined by the IEEE standard.

The IEEE rounding mode that specifies that the result of an operation should be the representable value closest to positive infinity (that is, the algebraically greater value).

The IEEE rounding mode that specifies that the result of an operation should be the representable value closest to negative infinity (that is, the algebraically lesser value).

The IEEE rounding mode that specifies that the result of an operation should be the representable value closest to zero (that is, the value with the smaller magnitude).

The act of choosing a representable value when the exact value produced by a floating-point operation is not representable. The IEEE standard specifies four methods of rounding, called rounding modes. See also rounding error.

The error that occurs when the result of an operation is rounded to the nearest representable value using an algorithm specified by the rounding mode.

One of four rounding methods specified by the IEEE standard: round to nearest (the default), round toward +INFINITY, round toward -INFINITY, and round toward zero.

A collection of object modules. When the linker scans a shared library, it does not copy modules into the application's code section, as it does with an archive library. Instead, the linker preserves information in the application's code section about which unresolved references were resolved in each shared library. At run time, the shared library is mapped into memory.

In a floating-point representation, the bit that indicates the sign of the value. In IEEE formats, the sign bit is the leftmost bit. See also exponent, fraction.

See trap handler.

A NaN (Not-a-Number) that generates an invalid operation condition whenever it is used. On HP 9000 systems, an SNaN has the most significant bit of the fraction set to 1. See also quiet NaN (QNaN).

See fraction.

An IEEE floating-point format in which the value occupies 32 bits: 1 bit for the sign, 8 bits for the exponent, and 23 bits for the fraction. See also double-precision, quad-precision.

See signaling NaN (SNaN).

One of the basic operations defined by the IEEE standard.

A variable that retains its value between invocations of the routine in which it is declared. From a performance standpoint, static variables are costly because they prohibit the compiler from making certain types of optimizations.

See exception flags.

See denormalized value.

One of the basic operations defined by the IEEE standard.

See flush-to-zero mode.

Rearranging the implementation of your algorithms to process as much data as possible while the data is resident in the cache so as to minimize the number of times the data must be re-cached later. See also cache aliases.

A hardware unit that serves as a cache for virtual-to-absolute memory address mapping.

A change in a program's flow of control due to the occurrence of an exception condition.

A routine that is invoked whenever a particular exception condition is detected, if the trap is enabled.

The rightmost bit of a floating-point representation. ULPs measure the distance between two numbers in terms of their representation in binary. One ULP is the distance from one value to the next representable value in the direction away from 0. See also precision.

The exception condition that occurs when a floating-point operation attempts to produce a result that may suffer extraordinary loss of accuracy because it is smaller in magnitude than the smallest normalized value.

In comparison operations, the relation that exists between two operands if one or both of them is a NaN (Not-a-Number); one is neither less than, equal to, nor greater than the other.

The replacement of a section of code that contains operations on arrays with a call to a special library routine. The compiler attempts automatic vectorization when invoked with appropriate options.

A floating-point value that is represented by a sign bit, a fraction that is all zeros, and an exponent that is all zeros. A zero has a magnitude less than any denormalized value.