Hewlett-Packard's nonscalable SMPs are single-node,
shared-memory machines that have a single level of memory latency.
Processors communicate with each other, with memory, and with peripherals
via a bus. Figure 2-1 “Nonscalable SMP overview” gives an
overview of a nonscalable SMP.
Memory |
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Memory is discussed in terms of physical memory and virtual
memory. The following two sections describe these types of memories
for nonscalable SMPs.
Memory configurations on HP's nonscalable SMPs varies
widely by machine. However, each of these machines uses memory interleaving
to improve performance. For an explanation, see the section “Interleaving”.
HP-UX 11.0 provides variable-sized pages to improve performance.
For more information on this feature, see the section “Variable-sized pages”.
Virtual memory is divided into five classes. For nonscalable
SMPs, only two of these classes are needed: thread_private
and node_private. The three remaining
classes are automatically mapped to the node_private
class.
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 | NOTE: For applications that will be ported to Hewlett-Packard
scalable SMPs, all five virtual memory classes can be useful. For
information on using the memory classes on a scalable SMP, see the
section “Virtual memory”. |
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A brief description of the virtual memory classes follow:
- thread_private
This memory is private to each thread of a process.
A thread_private data object has
a unique virtual address for each thread. These addresses map to
unique physical addresses in physical memory. Threads access the
physical copies of thread_private
data when they access thread_private
virtual addresses.
- node_private
This memory is shared among the threads running
on a hypernode. (For nonscalable SMPs, a hypernode
is the set of processors and physical memory.) Data objects of the
class node_private have a single
virtual address by which they can be accessed from any processor
in the hypernode.
- near_shared
This memory class is mapped to the node_private
memory class for nonscalable SMPs.
- far_shared
This memory class is mapped to the node_private
memory class for nonscalable SMPs.
- block_shared
This memory class is mapped to the node_private
memory class for nonscalable SMPs.
Data caches |
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Hewlett-Packard systems use caches to enhance performance.
Cache sizes, as well as cache line sizes, vary with the processor
used. Data is moved between the cache and memory using cache lines. A cache line describes the size of a chunk
of contiguous data that must be copied into or out of a cache in
one operation.
When a processor experiences a cache miss—that is,
requests data that is not already encached—the cache line
containing the address of the requested data is moved to the cache.
This cache line also contains a number of other data objects that
were not specifically requested.
One reason cache lines are employed is to allow for data
reuse. Data in a cache line is subject to reuse if,
while the line is encached, any of the data elements contained in
the line besides the originally requested element are referenced
by the program, or if the originally requested element is referenced
more than once.
Because data can only be moved to and from memory as part
of a cache line, both load and store operations cause their operands
to be encached. Cache-coherency hardware invalidates cache lines
in other processors when they are stored to by a particular processor.
This indicates to other processors that they must load the cache
line from memory the next time they reference its data.
For information on avoiding inefficient use of data, see the
section “Cache thrashing”.
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