+O1 level optimizations

At optimization level +O1, the compiler performs optimizations on a block level. The compiler also continues to perform the optimizations performed at +O0.

The +O1 optimizations are:

Branch optimization

The branch optimization involves traversing the procedure and transforming branch instruction sequences into more efficient sequences where possible. Examples of possible transformations are:

Deleting branches whose target is the fall-through instruction (in other words, the target is two instructions away).
Changing the target of the first branch to be the target of the second (unconditional) branch when the target of a branch is an unconditional branch.
Transforming an unconditional branch at the bottom of a loop that branches to a conditional branch at the top of the loop into a conditional branch at the bottom of the loop.
Changing an unconditional branch to the exit of a procedure into an exit sequence where possible.
Changing conditional or unconditional branch instructions that branch over a single instruction into a conditional nullification in the following instruction.
Looking for conditional branches over unconditional branches, where the sense of the first branch could be inverted and the second branch deleted. These result from null THEN clauses and from THEN clauses that only contain GOTO statements.
For example, in the following Fortran example:

      IF (L) THEN
        A=A*2
      ELSE
        GOTO 100
      ENDIF
      B=A+1
100   C=A*10

becomes:

      IF (.NOT. L) GOTO 100
      A=A*2
      B=A+1
100   C=A*10

Dead code elimination

Dead code elimination removes unreachable code that is never executed.

For example, in C:

if(0) 
  a = 1;
else 
  a = 2;

becomes:

a = 2;

Faster register allocation

Faster register allocation involves:

Inserting entry and exit code
Generating code for operations such as multiplication and division
Eliminating unnecessary copy instructions
Allocating actual registers to the dummy registers in instructions

Faster register allocation, when used at +O0 or +O1, analyzes register use faster than the global register allocation performed at +O2.

Instruction scheduler

The instruction scheduler optimization performs the following:

Reordering the instructions in a basic block to improve memory pipelining. For example, where possible, a load instruction is separated from the use of the loaded register.
Following a branch instruction with an instruction that can be executed as the branch occurs, where possible.
Scheduling floating-point instructions.

Peephole optimizations

A peephole optimization is a machine-dependent optimization that makes a pass through low-level assembly-like instruction sequences of the program, applying patterns to a small window (peephole) of code looking for optimization opportunities. The optimizations performed are:

Changing the addressing mode of instructions so they use shorter sequences
Replacing low-level assembly-like instruction sequences with faster (usually shorter) sequences, and removing redundant register loads and stores

+O1 level optimizations

Technical documentation

» Table of Contents

» Glossary

Branch optimization

Dead code elimination

Faster register allocation

Instruction scheduler

Peephole optimizations