Poll Word |
 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved (0) | AZR | AZT | 0 | CWEN | RSIG | DSIG | RTS | Reserved (0) |
All reserved bit positions
must be filled with zeros (0). |
AZR - (Z7340A only) Analyzer terminal for received
data
Enables this terminal for monitoring frames received on the
port. All received frames are copied, and the copy delivered to
the receiving application for this terminal. This terminal cannot
be used to transmit frames.
AZT - (Z7340A only) Analyzer terminal for transmitted
data
Enables this terminal for monitoring frames transmitted on
the port. All transmitted frames are copied, and the copy delivered
to the receiving application for this terminal. This terminal cannot
be used to transmit frames.
RSIG - Report status on CTS or DCD signal state change
If set to one (1), this bit enables an unsolicited status
message to be delivered to the receiving application when either
of the CTS or DCD signals is dropped, and when both CTS and DCD
are raised.
If this bit is set to zero (0), the HDLC.FRAME terminal does
not report the state of the CTS and DCD signals.
DSIG - Go down on loss of signal
If set to one (1), this bit will cause the HDLC.FRAME terminal's
status to be changed to DOWN when the CTS or DCD signal is lost.
At the same time, an unsolicited status message is delivered to
the receiving application. The RSIG option has no effect in this
case.
If this bit is set to zero (0), then the HDLC.FRAME terminal
continues to operate whatever the state of the CTS and DCD signals.
RTS - Control the RTS signal on transmitted frames
If set to one (1), this bit will cause the RTS signal to be
raised when the HDLC.FRAME terminal has a frame to transmit. When
CTS is raised by the remote device, the frame is transmitted after
frame transmission RTS is dropped, unless there is another frame
to transmit.
If this bit is set to zero (0), then RTS is kept raised as
long as the HDLC.FRAME terminal is enabled.
Select Word |
 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved (0) | BADFR | Reserved (0) |
All reserved bit positions
must be filled with zeros (0). |
BADFR - Bad frame completion
If set to one (1), this bit causes received frames with bad
CRC or received aborted frames to be passed up to the receiving
application with a status code indicating the error condition.
If this bit is set to zero (0), then all received frames with
bad CRC or received aborted frames are discarded.
The option word is not used with the HDLC.FRAME protocol.